Semiconductor memory device including a contact with different upper and bottom surface diameters and manufacturing method thereof
View Patent ↗A semiconductor memory device includes diffusion regions formed in an active region; cell contacts connected to the diffusion regions, respectively; pillars connected to the cell contacts, respectively; a bit line connected to the pillar; capacitor contacts connected to the pillars, respectively; and storage capacitors connected to the capacitor contacts, respectively. Accordingly, the pillars exist between the cell contacts and the capacitor contacts, and thus, depths of the capacitor contacts are made correspondingly shorter. Therefore, it becomes possible to prevent occurrence of shorting defects while decreasing resistance values of the capacitor contacts.
1. A method of manufacturing a semiconductor memory device, comprising:
forming a transistor including first and second diffusion regions;
forming first and second cell contacts connected to the first and second diffusion regions, respectively;
forming first and second pillars connected to the first and second cell contacts, respectively;
forming a bit line connected to the first pillar;
forming a capacitor contact connected to the second pillar; and
forming a storage capacitor connected to the capacitor contact,
wherein a diameter of at least one of an upper surface portion of the first pillar and an upper surface portion of the second pillar is smaller than a diameter of a bottom surface portion of the first pillar and a bottom surface portion of the first portion of the second pillar, respectively, wherein the upper surface portion of the first pillar is a surface portion that contacts the bit line, the upper surface portion of the second pillar is a surface portion that contacts the capacitor contact, the bottom surface portion of the first pillar is a surface portion that is opposite to the upper surface portion of the bit contact, and the bottom surface portion of the second pillar is a surface portion that is opposite to the upper surface portion of the second pillar.
2. The method of manufacturing a semiconductor memory device as claimed in claim 1 , wherein the forming the first and second pillars comprises patterning a metal material to form the first and second pillars.
3. The method of manufacturing a semiconductor memory device as claimed in claim 1 , wherein the bit line is formed by a damascene method.
4. The method of manufacturing a semiconductor memory device, the method comprising: a first step for forming a transistor including first and second diffusion regions;
a second step for simultaneously forming first and second cell contacts connected to the first and second diffusion regions, respectively;
a third step for simultaneously forming first and second pillars connected to the first and second cell contacts, respectively;
a fourth step for forming a bit line connected to the first pillar;
a fifth step for forming a capacitor contact connected to the second pillar; and
a sixth step for forming a storage capacitor connected to the capacitor contact,
the method further comprising: after the second step and before the third step,
a step for forming concave portions by over-etching the first and second cell contacts; and
a step for burying a metal material into the concave portions,
wherein at the third step a metal material is patterned to form the first and second pillars.
5. A method of manufacturing a semiconductor device, the method comprising:
forming first and second contacts over a substrate, the first contact being apart from the second contact and each of the first and second contacts having a top surface;
forming a first conductive line in contact with at least a part of the top surface of the first contact, the first conductive line having a top surface; and
forming a third contact in contact with at least a part of the top surface of the second contact, the third contact having a top surface that is different in level from the top surface of the first conductive line,
wherein the diameter of at least one of the top surface of the first contact and the top surface of the second contact is smaller than the diameter of a bottom surface of the first contact and a bottom surface of the second contact, respectively, wherein the bottom surface of the first contact is a surface that is opposite to the top surface of the first contact, and the bottom surface of the second contact is a surface that is opposite to the top surface of the second contact.
6. The method as claimed in claim 5 , wherein the forming the first and second contacts comprises forming a conductive layer and selectively removing the conductive layer to form the first and second contacts.
7. The method as claimed in claim 6 , further comprising forming a first insulating layer over the first and second contacts and filling a gap between the first and second contacts with the first insulating layer, and forming a first hole in the first insulating film to expose the part of the top surface of the first contact, the first conductive line being in contact with the part of the first contact through the first hole.
8. The method as claimed in claim 5 , further comprising forming an insulating layer over the second contact and the first conductive line and forming a hole in the insulating layer to expose the part of the top surface of the second contact, the third contact being in contact with the part of the top surface of the second contact through the hole.
9. A method comprising:
forming first and second contacts over a substrate, the first contact being apart from the second contact and each of the first and second contacts having a top surface;
forming a first conductive line in contact with at least a part of the top surface of the first contact, the first conductive line having a top surface;
forming a third contact in contact with at least a part of the top surface of the second contact, the third contact having a top surface that is different in level from the top surface of the first conductive line;
forming a first insulating layer over the first and second contacts and filling a gap between the first and second contacts, and forming a first hole in the first insulating film to expose the part of the top surface of the first contact, the first conductive line being in contact with the part of the first contact through the first hole; and
forming a second insulating layer over the first conductive line and the first insulating layer and forming a second hole in the second insulating layer to expose the part of the top surface of the second contact, the third contact being in contact with the part of the top surface of the second contact through the second hole,
wherein the forming the first and second contacts comprises forming a conductive layer and selectively removing the conductive layer to form the first and second contacts.
10. A method of manufacturing a semiconductor device, the method comprising:
forming a bit contact;
forming a bit line in contact with the bit contact;
forming a capacitor contact; and
forming a capacitor in contact with the capacitor contact; wherein
the forming the capacitor contact comprising forming a first portion of the capacitor contact simultaneously with the bit contact and forming a second portion of the capacitor contact after forming the bit line, wherein a diameter of at least one of an upper surface portion of the bit contact and an upper surface portion of the first portion of the capacitor contact is smaller than a diameter of a bottom surface portion of the bit contact and a bottom surface portion of the first portion of the capacitor contact, respectively, wherein the upper surface portion of the bit contact is a surface portion that contacts the bit line, the upper surface portion of the first portion of the capacitor contact is a surface portion that contacts the second portion of the capacitor contact, the bottom surface portion of the bit contact is a surface portion that is opposite to the upper surface portion of the bit contact, and the bottom surface portion of the first portion of the capacitor contact is a surface portion that is opposite to the upper surface portion of the first portion of the capacitor contact.
11. The method as claimed in claim 10 , wherein the forming the first portion of the capacitor contact simultaneously with the bit contact comprises forming a conductive layer, and patterning the conductive layer to form the bit contact and the first portion of the capacitor contact.
12. The method as claimed in claim 11 , further comprising forming a first insulating layer over the bit contact and the first portion of the capacitor contact, and forming a first hole of the first insulating layer to expose a part of the bit contact, the bit line being in contact with the exposed part of the bit contact though the first hole.
13. The method as claimed in claim 12 , further comprising forming a second insulating layer over the first insulating layer and the bit line, and forming a second hole in the second insulating layer to expose a part of the first portion of the capacitor contact, the second portion of the capacitor contact being in contact with the first portion of the capacitor contact exposed through the second hole.