IP Library Granted Patent US 7,710,095
Granted Patent B2
US 7,710,095 · App. 12/024,679 · Granted May 4, 2010

Power converter having PWM controller for maximum output power compensation

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Quick Facts
Patent No.
US 7,710,095
App. No.
12/024,679
Granted
May 4, 2010
Kind
B2
Abstract

A PWM controller compensates a maximum output power of a power converter having a power switch. The PWM controller includes an oscillator for generating a saw signal and a pulse signal, a power limiter coupled to the oscillator for generating a saw-limited signal in response to the saw signal, and a PWM unit coupled to the power limiter and the oscillator to generate a PWM signal for controlling the power switch in response to the saw-limited signal and the pulse signal. The saw-limited signal has a level being flattened during a period of time before an output voltage is generated, and is then transformed to a saw-limited waveform after the period of time.

Claims (48)

1. A PWM controller for compensating a maximum output power of a power converter including a power switch, comprising:

an oscillator for generating a saw signal and a pulse signal;

a power limiter coupled to the oscillator for generating a saw-limited signal in response to the saw signal; and

a PWM unit coupled to the power limiter and the oscillator to generate a PWM signal for controlling the power switch in response to the saw-limited signal and the pulse signal;

wherein the saw-limited signal has a level being flattened during a period of time before an output voltage is generated, and is then transformed to a saw-limited waveform after the period of time.

2. The PWM controller of claim 1 , wherein the power limiter comprises:

a delay unit for generating a control signal for controlling the waveform of the saw-limited signal; and

a saw-limited circuit coupled to the delay unit and the oscillator for receiving the control signal and the saw signal and generating the saw-limited signal in response to states of the control signal.

3. The PWM controller of claim 2 , wherein the saw-limited circuit comprises:

a first reference circuit for generating a first reference signal;

a second reference circuit coupled to the delayed unit for receiving the control signal and providing a second reference signal in response to the control signal; and

a current limited circuit coupled to the oscillator, the delay unit, the first reference circuit and the second reference circuit for generating the saw-limited signal in response to the saw signal, the first reference signal, the second reference signal and the control signal.

4. The PWM controller of claim 2 , wherein the delay unit comprises:

a delay counter for generating a delay signal in response to an enabling of a voltage source; and

an inverter coupled to the delay counter for inverting the delay signal and generating the control signal.

5. The PWM controller of claim 2 , wherein the delay unit comprises:

a negative delta V counter for generating a delay signal when detecting a negative delta V signal, wherein the delay signal is enabled once the output voltage is generated and a feedback voltage starts to decrease; and

an inverter coupled to the negative delta V counter for inverting the delay signal and generating the control signal.

6. The PWM controller of claim 2 , wherein the delay unit comprises:

a delay counter for generating a delay signal in response to a voltage source;

an inverter coupled to the delay counter for inverting the delay signal to generate an inverted delay signal;

a comparison circuit for generating a comparison signal in response to a comparison between a feedback voltage and a reference voltage; and

a logic unit for generating the control signal in response to the inverted delay signal and the comparison signal.

7. A power converter, comprising:

a power switch for controlling a current flow through a transformer;

a PWM controller for generating a PWM signal for controlling the power switch to switch the transformer, wherein the PWM controller comprises:

an oscillator for generating a saw signal and a pulse signal;

a power limiter coupled to the oscillator for generating a saw-limited signal in response the saw signal; and

a PWM unit coupled to the power limiter and the oscillator for generating the PWM signal for controlling the power switch in response to the saw-limited signal and the pulse signal;

wherein the saw-limited signal has a level being flattened during a period of time before an output voltage is generated, and is then transformed to a saw-limited waveform after the period of time.

8. The power converter of claim 7 , wherein the power limiter comprises:

a delay unit for generating a control signal for controlling the waveform of the saw-limited signal; and

a saw-limited circuit coupled to the delay unit and the oscillator for receiving the control signal and the saw signal and generating the saw-limited signal in response to states of the control signal.

9. The power converter of claim 8 , wherein the saw-limited circuit comprises:

a first reference circuit for generating a first reference signal;

a second reference circuit coupled to the delayed unit for receiving the control signal and providing a second reference signal in response to the control signal; and

a current limited circuit coupled to the oscillator, the delay unit, the first reference circuit, and the second reference circuit for generating the saw-limited signal in response to the saw signal, the first reference signal, the second reference signal and the control signal.

10. The power converter of claim 8 , wherein the delay unit comprises:

a delay counter for generating a delay signal in response to an enabling of a voltage source; and

an inverter coupled to the delay counter for inverting the delay signal to generate the control signal.

11. The power converter of claim 8 , wherein the delay unit comprises:

a negative delta V counter for generating a delay signal when detecting a negative delta V signal, wherein the delay signal is enabled once the output voltage is generated and a feedback voltage starts to decrease; and

an inverter coupled to the negative delta V counter for inverting the delay signal to generate the control signal.

12. The power converter of claim 8 , wherein the delay unit comprises:

a delay counter for generating a delay signal in response to a voltage source;

an inverter coupled to the delay counter for inverting the delay signal to generate an inverted delay signal;

a comparison circuit for generating a comparison signal in response to a comparison between a feedback voltage and a reference voltage; and

a logic unit for generating the control signal in response to the inverted delay signal and the comparison signal.

Assignments (5)
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT RECORDED AT REEL 046410, FRAME 0933 Recorded Jun 22, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 064072/0001 →
PATENT SECURITY AGREEMENT Recorded Jun 22, 2018
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 046410/0933 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 25, 2017
From: FAIRCHILD (TAIWAN) CORPORATION (FORMERLY SYSTEM GENERAL CORPORATION)
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 042328/0318 →
CHANGE OF NAME Recorded May 3, 2016
From: SYSTEM GENERAL CORPORATION
To: FAIRCHILD (TAIWAN) CORPORATION
Reel/Frame 038599/0043 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 1, 2008
From: HUANG, WEI-HSUAN; LIN, CHIEN-YUAN; HSUEH, CHENG-CHI
To: SYSTEM GENERAL CORPORATION
Reel/Frame 020456/0859 →