DEVICE FOR CHECKING NUMBERS AND METHOD FOR CHECKING NUMBERS
A device for checking numbers consists of a multiplexer ( 101 ) with a controller module ( 106 ) linked to it. An output of the multiplexer is connected to a first input of a register ( 102 ), which is an element of memory, while a first output of the controller module ( 106 ) is connected to an input of a memory ( 103 ) and a second input of the register ( 102 ). An output of the register ( 102 ) and an output of the memory ( 103 ) are connected to inputs of the adder ( 104 ), which adds on its output a number, stored in the register ( 102 ) and a number written in the memory ( 103 ) at an address indicated by the controller module ( 106 ). The adder ( 104 ) generates on its output a carry-out signal, informing about overflow, which is passed to a first controlling input of the controller module ( 106 ), which manages operation of the device checking numbers. A second controlling input of the controller module ( 106 ) is coupled a logical NOR type gate ( 105 ) passing a zero signal informing that the number on the output of the adder ( 104 ) equals zero.
1 . A device for checking n-bit numbers comprising
a multiplexer having a first multiplexer input for receiving an input number, a second multiplexer input for receiving a number, a controlling input and a multiplexer output;
a controller module comprising a first controlling input, a first controlling output connected to the controlling input of the multiplexer, a second controlling output and a controller module output;
a register for storing a multiplexer output number output by the multiplexer and having a controlling input connected to the second controlling output of the controller module, a register input connected to the multiplexer output and a register output;
a memory for storing information related to a range of input numbers, the memory having a storage input connected to the controller module output and a storage output; and
an (n+i)-bit adder comprising a first adder input connected to the register output, a second adder input connected to the storage output of the memory, an adder output and a carry-out output wherein the adder adds the number stored in the register and a number stored in the memory at an address indicated by the controller module, and outputs a result of addition via the adder output, to the second multiplexer input and generates at the carry-out output a carry-out signal informing about carry-out and being passed to the first controlling input of the controller module.
2 . The device of claim 1 , wherein the adder further outputs a zero signal when the result of addition equals 0.
3 . The device of claim 2 , wherein the controller module comprises a second controlling input for receiving the zero signal.
4 . The device of claim 1 , wherein the controller module stores the carry value output by the adder.
5 . The device of claim 1 , wherein the n+i equals n+1.
6 . The device of claim 1 , wherein the memory stores a correction coefficient.
7 . The device of claim 6 , wherein the controller module causes modification of the input number by the correction coefficient when the input number is within the range.
8 . A method of checking n-bit numbers, the method comprising the steps of:
obtaining a lower limit and an upper limit of a range;
computing an (n+i)-bit lower coefficient as (−(the lower limit));
computing an (n+i)-bit upper coefficient as (−((the upper limit)−(the lower limit)));
calculating by an (n+i)-bit adder a first sum by adding the lower coefficient and an input number;
storing a first carry-out value of the first sum;
calculating a second sum by adding the upper coefficient and the first sum;
storing a second carry-out value of the second sum; and
determining that the input number is within the range when the first carry-out value of the first sum signals overflow and the second carry-out value of the second sum does not signal overflow.
9 . The device of claim 1 , wherein the n+i equals n+1.
10 . The method of claim 8 wherein more than one range is checked against the input number.
11 . The method, of claim 8 , wherein in order to check if the n-bit input number is equal to the lower limit or the upper limit of the range, it is checked whether the first sum or the second sum equals 0.
12 . The method, of claim 8 , further comprising the step of changing the n-bit input number by a correction coefficient when the number is within the range.
13 . The method, of claim 8 , further comprising the steps of changing the n-bit input number by a correction coefficient when the first sum or the second sum equals zero.
14 . The method, of claim 8 , further comprising the steps of defining a sequential correction coefficient, checking sequentially further ranges of the ranges of input numbers and changing the n-bit input number by the sequential correction coefficient when the number is within the range.
15 . The method, of claim 12 , wherein the correction coefficient equals ((correction value)+(upper limit)).
16 . The method of claim 14 , wherein values of each range are stored in a sequence and at increasing addresses of the memory wherein a first value of the sequence is the lower coefficient, a second value of the sequence is the upper coefficient and a third value of the sequence is the correction coefficient.
17 . The method of claim 8 , wherein n equals 13.