Leakage barrier for GaN based HEMT active device
View Patent ↗An improved HEMT formed from a GaN material system is disclosed which has reduced gate leakage current relative to known GaN based HEMTs and eliminates the problem of current constrictions resulting from deposition of the gate metal over the step discontinuities formed over the gate mesa. The HEMT device is formed from a GaN material system. One or more GaN based materials are layered and etched to form a gate mesa with step discontinuities defining source and drain regions. In order to reduce the leakage current, the step discontinuities are back-filled with an insulating material, such as silicon nitride (SiN), forming a flat surface relative to the source and drain regions, to enable to the gate metal to lay flat. By back-filling the source and drain regions with an insulating material, leakage currents between the gate and source and the gate and drain are greatly reduced. In addition, current constrictions resulting from the deposition of the gate metal over a step discontinuity are virtually eliminated.
1. A process for forming a high electron mobility transistor (HEMT) comprising:
(a) providing a substrate;
(b) depositing one or more Gallium Nitride (GaN) based materials on said substrate;
(c) forming a mesa on said substrate with said GaN based materials which defines a gate region on top of said mesa and drain and source regions on opposing sides next to said mesa on said substrate, said mesa defining vertical sidewalls between said gate region and said drain and source regions and forming steps on opposing sides of said mesa;
(d) depositing insulation on said substrate in said drain and source regions so that it is flush with the top of the mesa and flush with said vertical sidewalls, thereby eliminating said steps between said gate region and said drain and source regions; and
(e) forming gate metal on a portion of said gate region defining a gate contact and exposed portions on opposing sides of said gate contact; and
(f) forming source and drain contacts on said insulation in said drain and source regions and in contact with said exposed portions of said gate region.
2. The process as recited in claim 1 , wherein said GaN based material includes bulk GaN.
3. The process as recited in claim 1 , wherein said GaN based material includes GaN and aluminum gallium nitride (AIGaN).
4. The process as recited in claim 3 , wherein the step of depositing one or more GaN based materials comprises:
depositing a GaN layer on top of said substrate;
depositing a buffer layer of AIGaN on top of said GaN layer; and
depositing a top GaN layer on top of said buffer layer.
5. The process as recited in claim 1 , wherein said insulating material is silicon nitride (SiN).
6. The process as recited in claim 1 , wherein step (e) comprises:
(e1) depositing gate metal on said mesa in said gate region and on said insulation disposed in said drain and source regions;
(e2) removing said gate metal from portions of said gate region adjacent said drain and source regions defining exposed gate portions and from said drain and source regions.