Methods and apparatus for layout of multi-layer circuit substrates
View Patent ↗Methods and apparatus are provided for designing and laying out multi-layer circuit substrates, such as multi-layer PCBs. Dynamic vias are provided on intermediate PCB layers. Each dynamic via has features that adjust based on the trace layout of the corresponding intermediate layer. In particular, each dynamic via has a second radius R 2 if the via is not connected to any trace on the corresponding intermediate layer. If a trace is connected to a dynamic via, the via radius changes from the second radius R 2 to a first radius R 1 , where R 1 is greater than R 2.
1. A method for laying out a layer of a multi-layer circuit substrate, the method comprising:
providing a via that has a center axis and a second radius R 2 ;
adding a pad and changing the via radius from the second radius to a first radius R 1 for a first trace connected to the via on an intermediate layer, where R 1 is greater than R 2 ;
providing a second trace that has a width W and a center axis; and
calculating a first minimum separation S 1 =(R 1 +d 1 +W/2), and a second minimum separation S 2 =(R 2 +d 1 +W/2), wherein d 1 is a minimum trace-to-pad air gap d 1 .
2. The method of claim 1 , wherein the multi-layer circuit comprises an integrated circuit.
3. The method of claim 1 , wherein the circuit comprises a printed circuit board.
4. The method of claim 1 , further comprising:
if the via has a pad on the layer, laying out the second trace center axis no closer than a first minimum separation S 1 from the via center axis; and
if the via has no pad on the layer, laying out the second trace center axis no closer than a second minimum separation S 2 from the via center axis.
5. The method of claim 1 , wherein if the via has a connected pad on the layer, laying out the second trace center axis substantially at the first minimum separation S 1 from the via center axis.
6. The method of claim 1 , wherein if the via has an unconnected pad on the layer, laying out the second trace center axis substantially at the second minimum separation S 2 from the via center axis.
7. A method for laying out a plurality of traces on a layer of a multi-layer circuit comprising first and second vias separated by a pitch P, each via having a first radius R 1 and a second radius R 2 , each trace having a minimum width W, and wherein a design rule for the circuit specifies a minimum trace-to-pad air gap d 1 and a minimum trace-to-trace air gap d 2 , the method comprising:
calculating a first available space between the first and second vias using the first radius R 1 ;
calculating a second available space between the first and second vias using the second radius R 2 ;
calculating a third available space between the first and second vias using the first radius R 1 and the second radius R 2 ;
if the first and second vias each have a connected pad on the layer, calculating a first number of minimum-width traces that can be laid out using the first available space, and communicating to a user the first number of minimum-width traces;
if the first and second vias each have no connected pad on the layer, calculating a second number of minimum-width traces that can be laid out using the second available space, and communicating to the user the second number of minimum-width traces; and
if one of the first or second vias has a connected pad on the layer, and the other of the first or second vias does not have a connected pad on the layer, calculating a third number of minimum-width traces that can be laid out using the third available space, and communicating to the user the third number of minimum-width traces.
8. The method of claim 7 , wherein the first number of minimum-width traces that can be laid out using the first available space is less than or equal to:
(
P
-
2
×
R
1
-
2
×
d
1
+
d
2
)
(
W
+
d
2
)
.
9. The method of claim 7 , wherein the second number of minimum-width traces that can be laid out using the second available space is less than or equal to:
(
P
-
2
×
R
2
-
2
×
d
1
+
d
2
)
(
W
+
d
2
)
.
10. The method of claim 7 , wherein the third number of minimum-width traces that can be laid out using the third available space is less than or equal to:
(
P
-
R
1
-
R
2
-
2
×
d
1
+
d
2
)
(
W
+
d
2
)
.
11. A physical, non-transitory computer-readable carrier including computer program instructions for laying out a layer of a multi-layer circuit substrate, the computer program instructions configured to cause a computer to:
provide a via that has a center axis and a second radius R 2 ;
add a pad and change the via radius from the second radius to a first radius R 1 for a first trace connected to the via on an intermediate layer, where R 1 is greater than R 2 ;
provide a second trace that has a width W and a center axis; and
calculate a first minimum separation S 1 =(R 1 +d 1 +W/2), and a second minimum separation S 2 =(R 2 +d 1 +W/2), wherein d 1 is a minimum trace-to-pad air gap d 1 .
12. The physical computer-readable carrier of claim 11 , wherein the multi-layer circuit comprises an integrated circuit.
13. The physical computer-readable carrier of claim 11 , wherein the circuit comprises a printed circuit board.
14. The physical computer-readable carrier of claim 11 , wherein the computer program instructions are further configured to cause the computer to:
lay out the second trace center axis no closer than a first minimum separation S 1 from the via center axis if the via has a pad on the layer; and
lay out the second trace center axis no closer than a second minimum separation S 2 from the via center axis if the via has no pad on the layer.
15. The physical computer-readable carrier of claim 11 , wherein the computer program instructions are further configured to cause the computer to lay out the second trace center axis substantially at the first minimum separation S 1 from the via center axis if the via has a connected pad on the layer.
16. The physical computer-readable carrier of claim 11 , wherein the computer program instructions are further configured to cause the computer to lay out the second trace center axis substantially at the second minimum separation S 2 from the via center axis if the via has an unconnected pad on the layer.
17. A physical, non-transitory computer-readable carrier including computer program instructions for laying out a plurality of traces on a layer of a multi-layer circuit comprising first and second vias separated by a pitch P, each via having a first radius R 1 and a second radius R 2 , each trace having a minimum width W, and wherein a design rule for the circuit specifies a minimum trace-to-pad air gap d 1 and a minimum trace-to-trace air gap d 2 , the computer program instructions configured to cause a computer to:
calculate a first available space between the first and second vias using the first radius R 1 ;
calculate a second available space between the first and second vias using the second radius R 2 ;
calculate a third available space between the first and second vias using the first radius R 1 and the second radius R 2 ;
if the first and second vias each have a connected pad on the layer, calculate a first number of minimum-width traces that can be laid out using the first available space, and communicating to a user the first number of minimum-width traces;
if the first and second vias each have no connected pad on the layer, calculate a second number of minimum-width traces that can be laid out using the second available space, and communicating to the user the second, number of minimum-width traces; and
if one of the first or second vias has a connected pad on the layer, and the other of the first or second vias does not have a connected pad on the layer, calculate a third number of minimum-width traces that can be laid out using the third available space, and communicating to the user the third number of minimum-width traces.
18. The physical computer-readable carrier of claim 17 , wherein the computer program instructions are further configured to cause the computer to calculate the first number of minimum-width traces that can be laid out using the first available space as less than or equal to:
(
P
-
2
×
R
1
-
2
×
d
1
+
d
2
)
(
W
+
d
2
)
.
19. The physical computer-readable carrier of claim 17 , wherein the computer program instructions are further configured to cause the computer to calculate the second number of minimum-width traces that can be laid out using the second available space as less than or equal to:
(
P
-
2
×
R
2
-
2
×
d
1
+
d
2
)
(
W
+
d
2
)
.
20. The physical computer-readable carrier of claim 17 , wherein the computer program instructions are further configured to cause the computer to calculate the third number of minimum-width traces that can be laid out using the third available space as less than or equal to:
(
P
-
R
1
-
R
2
-
2
×
d
1
+
d
2
)
(
W
+
d
2
)
.