Semiconductor device and manufacturing method thereof

1. A semiconductor device comprising:

a first MIS transistor; and

a second MIS transistor,

wherein

the first MIS transistor includes:

a first active region surrounded by an isolation region in a semiconductor substrate;

a first gate insulating film formed on the first active region; and

a first gate electrode including a first metal film formed on the first gate insulating film, and a first silicon film formed directly on the first metal film,

the second MIS transistor includes:

a second active region surrounded by the isolation region in the semiconductor substrate;

a second gate insulating film formed on the second active region and made of an insulating material different from that of the first gate insulating film; and

a second gate electrode including a second metal film formed on the second gate insulating film, and a second silicon film formed directly on the second metal film,

the isolation region has an isolation part located between the first active region and the second active region adjacent to each other along a gate width direction,

the first gate electrode and the second gate electrode extend on the isolation part,

the first gate electrode and the second gate electrode have opposing surfaces facing each other on the isolation part, a part of the opposing surface located in the first silicon film and a part of the opposing surface located in the second silicon film are connected to each other so that the first silicon film and the second silicon film are integrally formed with each other, and a part of the opposing surface located in the first metal film and a part of the opposing surface located in the second metal film are separated from each other with a sidewall insulating film interposed therebetween, the sidewall insulating film being integrally formed with the first gate insulating film, and being formed on the isolation part.

2. The semiconductor device of claim 1 , further comprising:

a first silicide layer formed on the first gate electrode; and

a second silicide layer formed on the second gate electrode.

3. The semiconductor device of claim 1 , further comprising:

a first sidewall formed on a side surface of the first gate electrode;

a first source/drain region formed outside the first sidewall in the first active region;

a second sidewall formed on a side surface of the second gate electrode; and

a second source/drain region formed outside the second sidewall in the second active region.

4. The semiconductor device of claim 3 , further comprising:

a third silicide layer formed on the first source/drain region; and

a fourth silicide layer formed on the second source/drain region.

5. The semiconductor device of claim 1 , wherein

the first MIS transistor is an N-type MIS transistor, and

the second MIS transistor is a P-type MIS transistor.

6. The semiconductor device of claim 1 , wherein

the sidewall insulating film is provided on a side surface of an edge portion of the second metal film in the second gate electrode in the gate width direction, the edge portion being located on the isolation part.

7. The semiconductor device of claim 1 , wherein

the sidewall insulating film is provided so as to be in contact with respective side surfaces of the first metal film and the second metal film.

8. The semiconductor device of claim 1 , wherein the sidewall insulating film has the same thickness as a thickness of the first gate insulating film.

9. The semiconductor device of claim 1 , wherein an upper surface of a part of the first metal film located above the first active region is higher than an upper surface of a part of the second metal film located above the second active region.

10. The semiconductor device of claim 1 , wherein an upper surface of a part of the first metal film located above the first active region is higher than an upper edge of the sidewall insulating film.

11. The semiconductor device of claim 1 , wherein a height of an upper surface of a part of the second metal film located above the second active region is substantially the same as that of the upper edge of the sidewall insulating film.

12. The semiconductor device of claim 1 , wherein a thickness of a part of the first silicon film located above the first active region is thinner than a thickness of a part of the second silicon film located above the second active region.

13. The semiconductor device of claim 1 , wherein

the first metal film is made of a TaSiN film, and

the second metal film is made of a TiN film.

14. The semiconductor device of claim 1 , wherein the first silicon film and the second silicon film are made of a P-doped polysilicon film.

15. The semiconductor device of claim 1 , wherein the first metal film and the second metal film are made of metal materials having different compositions or composition ratios.

16. The semiconductor device of claim 1 , wherein a metal material for the first metal film or the second metal film include any metal of aluminum (Al), titanium (Ti), tungsten (W), tantalum (Ta), and molybdenum (Mo), and nitrides, carbon nitrides or silicon nitrides of alloys of these metals.

17. The semiconductor device of claim 1 , wherein

the first gate insulating film is made of Hf 0.7 SiON, and

the second gate insulating film is made of Hf 0.5 SiON.

18. The semiconductor device of claim 1 , wherein

the first gate insulating film is made of HfAlSiON, and

the second gate insulating film is made of HfSiON.