Passivated Copper Chip Pads
A structure and method of forming passivated copper chip pads is described. In various embodiments, the invention describes a substrate that includes active circuitry and metal levels disposed above the substrate. A passivation layer is disposed above a last level of the metal levels. A conductive liner is disposed in the sidewalls of an opening disposed in the passivation layer, wherein the conductive liner is also disposed over an exposed surface of the last level of the metal levels.
1 - 16 . (canceled)
17 . A flip chip package comprising:
metallization comprising metal levels disposed above a substrate, the substrate comprising active circuitry;
a cap layer disposed above a last level of the metal levels;
a passivation layer disposed above the cap layer;
a nitride layer disposed above the passivation layer, wherein an opening is disposed in the nitride layer, the passivation layer and the cap layer; and
a conductive liner disposed in sidewalls of the opening and over an exposed surface of the last level of the metal levels.
18 . The flip chip package of claim 17 , wherein the conductive liner comprises a material selected from the group consisting of TiN, TaN, Ti/TiN, Ta, Ta/TaN, and Al/Cu.
19 . The flip chip package of claim 17 , wherein the passivation layer comprises an oxide layer.
20 . The flip chip package of claim 17 , wherein the last level of the metal levels comprises copper, wherein the last level of the metal levels is embedded in an inter level dielectric layer.
21 . The flip chip package of claim 17 , further comprising:
an under bump metallization layer disposed over the conductive liner; and
a solder bump disposed above the under bump metallization layer.
22 . The flip chip package of claim 21 , wherein the solder bump comprises an eutectic 63Sn:37Pb, 5Sn:95Pb, or an Sn:Ag alloy, and wherein the under bump metallization layer comprises layers comprising Ti/Cu/Ni.
23 . (canceled)
24 . A passivated copper chip pad comprising:
metallization comprising metal levels disposed above a substrate, the substrate comprising active circuitry;
a cap layer disposed above a last level of the metal levels;
a passivation layer disposed above the cap layer;
a nitride layer disposed above the passivation layer;
an opening disposed in the nitride layer, the passivation layer, and the cap layer; and
a conductive liner disposed in sidewalls of the opening and over an exposed surface of the last level of the metal levels.
25 . The passivated copper chip pad of claim 24 , further comprising:
an under bump metallization layer disposed over the conductive liner; and
a solder bump disposed above the under bump metallization layer.
26 . The passivated copper chip pad of claim 24 , wherein the last level of the metal levels comprises copper, wherein the last level of the metal levels is embedded in an inter level dielectric layer.
27 . The passivated copper chip pad of claim 24 , wherein the solder bump comprises an eutectic 63Sn:37Pb, 5Sn:95Pb, or an Sn:Ag alloy, and wherein the under bump metallization layer comprises layers comprising Ti/Cu/Ni.
28 . The flip chip package of claim 17 , wherein the cap layer comprises a nitride material.
29 . A flip chip package comprising:
metallization comprising metal levels disposed above a substrate, the substrate comprising active circuitry;
a cap layer disposed above a last level of the metal levels;
a passivation layer disposed above the cap layer;
an opening disposed in the passivation layer and the cap layer; and
a conductive liner disposed over the last level of the metal levels and along the sidewalls of the opening wherein the conductive liner extends above a top surface of the passivation layer and does not overlie a horizontal surface of the passivation layer.
30 . The flip chip package of claim 29 , wherein the conductive liner comprises a material selected from the group consisting of TiN, TaN, Ti/TiN, Ta, Ta/TaN, and Al/Cu.
31 . The flip chip package of claim 29 , wherein the passivation layer is selected from the group consisting of an oxide, FTEOS, SiN and SiCOH.
32 . The flip chip package of claim 29 , wherein the last level of the metal levels comprises copper, wherein the last level of the metal levels is embedded in an inter level dielectric layer.
33 . The flip chip package of claim 29 , further comprising:
an under bump metallization layer disposed over the conductive liner; and
a solder bump disposed above the under bump metallization layer.
34 . The flip chip package of claim 21 , wherein the solder bump is bonded to a PC board.