Semiconductor device
View Patent ↗Provided is a semiconductor device having a trench isolation structure and a high power supply voltage circuit section including at least a well region and a MOS transistor formed therein. The high power supply voltage circuit section includes a carrier capture region for preventing latch-up in a vicinity of an end portion of the well region, and a depth of the carrier capture region is larger than a depth of the trench isolation region. The carrier capture region in the high power supply voltage circuit section is formed of a diffusion layer which is the same as that of a source or a drain region of the MOS transistor formed in the high power supply voltage circuit section.
1. A semiconductor device comprising:
a high power supply voltage circuit section including a semiconductor substrate, a well region arranged in the semiconductor substrate, and a MOS transistor formed in the well region;
a low power supply voltage circuit section; and
a trench isolation structure in which element isolation in the high power supply voltage circuit section and the low power supply voltage circuit section is carried out by a trench isolation region;
wherein the high power supply voltage circuit section includes a carrier capture region for preventing latch-up in a vicinity of an end portion of the well region, and a depth of the carrier capture region is larger than a depth of the trench isolation region;
wherein a conductivity type of the carrier capture region is identical to the conductivity type of the well region within which the carrier capture region is present.
2. A semiconductor device according to claim 1 ,
wherein the semiconductor substrate has a first conductivity type and the well region comprises a first well of the first conductivity type and a second well of a second conductivity type, and
wherein the carrier capture region is present in each of an end portion of the first well and an end portion of the second well in a vicinity of a junction between the first well and the second well.
3. A semiconductor device according to claim 1 ,
wherein the semiconductor substrate has a first conductivity type; and the well region comprises a selected well of a second conductivity type, and
wherein the carrier capture region is present in each of the semiconductor substrate of the first conductivity type and the selected well in a vicinity of a junction between the semiconductor substrate of the first conductivity type and the selected well.
4. A semiconductor device according to claim 1 , wherein the semiconductor substrate has a first conductivity type, and the well region comprises a first well of the first conductivity type and a second well of a second conductivity type, and
wherein the carrier capture region is present only in an end portion of the first well in a vicinity of a junction between the first well and the second well has the carrier capture region.
5. A semiconductor device according to claim 1 ,
wherein the semiconductor substrate has a first conductivity type and the well region comprises a first well of the first conductivity types and a second well of a second conductivity type, and
wherein the carrier capture region is present only in an end portion of the second well in a vicinity of a junction between the first well and the second well has the carrier capture region.
6. A semiconductor device according to claim 1 ,
wherein the semiconductor substrate has a first conductivity type and the well region comprises a selected well of a second conductivity type, and
wherein the carrier capture region is present only in a side of the semiconductor substrate of the first conductivity type in a vicinity of a junction between the semiconductor substrate of the first conductivity type and the selected well.
7. A semiconductor device according to claim 1 ,
wherein the semiconductor substrate has a first conductivity types and the well region comprises a selected well of a second conductivity type, and
wherein the carrier capture region is present only in a side of the second well in a vicinity of a junction between the semiconductor substrate of the first conductivity type and the selected well.
8. A semiconductor device according to claim 1 , wherein the carrier capture region in the high power supply voltage circuit section is formed of a diffusion layer which is the same as that of one of a source and a drain region of the MOS transistor formed in the high power supply voltage circuit section.