Method and apparatus for ESD protection
View Patent ↗A technique that minimizes false triggering of an electrostatic discharge (ESD) protection circuit is disclosed. In an embodiment, the resistor-capacitor (RC) time constant of an ESD trigger element is reduced during normal operation minimizing the risk of false triggering. Circuit layout area is saved without the need of a timeout circuit associated with releasing a device maintaining a trigger state (i.e., a trigger latch). A RC time constant for triggering is set in an operational context according to conditions of usage and desired application of the ESD protection circuit.
1. An apparatus for providing electrostatic discharge (ESD) protection, the apparatus comprising:
a trigger stage having a trigger capacitor coupled to a trigger resistor, the trigger stage being coupled to a first inverter, the first inverter configured to control only a trigger shunt device;
the trigger stage being configured to respond to an ESD event; and
a second inverter coupled to the trigger stage and the first inverter, and to a trigger latch to control an ESD shunt device; and
wherein the trigger shunt device shunts the trigger resistor when an associated device coupled to the apparatus is powered.
2. The apparatus of claim 1 , wherein an RC time constant of the apparatus is substantially reduced by the trigger shunt device configured to shunt the trigger resistor.
3. The apparatus of claim 2 , wherein the RC time constant of the apparatus is configured to be substantially less than an expected rate of voltage fluctuation on a power terminal due to noise or simultaneous switching outputs produced by the associated device, the apparatus being responsive to the noise or simultaneous switching of outputs when the associated device is off.
4. The apparatus of claim 1 , wherein the trigger latch is configured to retain an indication of an ESD event being triggered.
5. The apparatus of claim 1 being configured to have an RC time constant selected to correspond with an expected time range of an ESD event.
6. The apparatus of claim 1 , wherein values of the trigger capacitor and the trigger resistor determine a predetermined RC time constant that corresponds with voltage characteristics related to an onset of an ESD event during a non-powered condition.
7. An apparatus comprising:
a capacitor and a resistor coupled in series between a power node and a ground node;
a first inverter having an input coupled to a node between the capacitor and the resistor;
a trigger shunt device having a gate coupled to an output of the first inverter, a drain coupled to the input of the first inverter, a source coupled to the ground node, and a region between the drain and the source coupled to the ground node, where the first inverter is configured to control only the trigger shunt device;
a second inverter having an input coupled to the input of the first inverter;
a latch coupled to an output of the second inverter; and
an electrostatic discharge shunt device coupled to the latch and coupled between the power node and the ground node.
8. The apparatus of claim 7 , wherein the trigger shunt device and the electrostatic discharge shunt device include a same type of transistors.
9. The apparatus of claim 7 , wherein the electrostatic discharge shunt device includes a gate coupled to the latch, a drain coupled to the power node, a source coupled to the ground node, and a region between the drain and the source coupled to the ground node.
10. The apparatus of claim 7 , wherein the first inverter includes a first transistor and a second transistor coupled in series between the power node and the ground node, the second transistor including a gate coupled to the input of the second inverter, a drain coupled to the gate of the trigger shunt device, a source coupled to the ground node, and a region between the drain and the source coupled to the ground node.
11. The apparatus of claim 7 , wherein the second inverter includes a third transistor and a fourth transistor coupled in series between the power node and the ground node, the fourth transistor including a gate coupled to the input of the first inverter, a drain coupled to the output of the second inverter, a source coupled to the ground node, and a region between the drain and the source coupled to the ground node.
12. The apparatus of claim 7 , wherein the latch includes a third inverter coupled between the power node and the ground node, a fourth inverter coupled between the power node and the ground node, the fourth inverter having an input coupled to an output of the third inverter and an output coupled to an input of the third inverter and to the gate of the electrostatic discharge shunt device.