Tamper Detection Line Circuitry For An Authentication Integrated Circuit

1 . Tamper detection line circuitry for an authentication integrated circuit for use in authenticating an integrated circuit, the tamper detection line circuitry comprising:

a source of pseudo-random bits;

an XOR gate with two inputs and an output in signal communication with flash memory erase and reset circuits, where a complete erasure is triggered by a 0 from the XOR gate;

first and second paths arranging the source and XOR gate in signal communication with each other, the first path connected to one input of the XOR gate and the second path having an inverter and connected to a second input of the XOR gate; and

a number of triggers connected to the respective paths, each trigger configured to detect a physical attack on the authentication integrated circuit.

2 . Tamper detection line circuitry as claimed in claim 1 , wherein each trigger includes an nMOS transistor attached to GND.

3 . Tamper detection line circuitry as claimed in claim 1 , wherein a transistor of a trigger is configured to pull the respective path to 0 if a physical attack is detected.

4 . Tamper detection line circuitry as claimed in claim 1 , wherein the source includes a noise generator circuit.

5 . Tamper detection line circuitry as claimed in claim 1 , wherein the source operates at a higher frequency than an operating frequency of the authentication integrated circuit.

6 . Tamper detection line circuitry as claimed in claim 1 , wherein wires representing the paths are positioned on a layer above the authentication integrated circuit.

7 . Tamper detection line circuitry as claimed in claim 4 , wherein the noise generator and inverter are positioned on one level, while the paths are positioned on a level above the generator.