Non-volatile semiconductor storage device
A non-volatile semiconductor storage device includes: one or more memory cells including anti-fuse elements capable of writing data by breaking down a gate insulation film of a MOS transistor with a high voltage; a sense node having its one end connected to each of the anti-fuse elements; a sense amplifier comparing the potential of the sense node with the reference potential and amplifying the difference therebetween, the sense amplifier being activated according to a sense-amplifier activation signal; an initialization circuit initializing the potential of the sense node according to an initialization signal; a control circuit outputting the initialization signal at a predetermined timing after input of an external signal input from the outside and outputting a first activation signal to activate the sense amplifier at a predetermined timing after input of the external signal; and a switching circuit outputting the first activation signal as the sense-amplifier activation signal when a normal data read operation is performed, and outputting an inverted version of the external signal as the sense-amplifier activation signal when a test execution is instructed for the one or more memory cells before the gate insulation film is broken down.
1. A non-volatile semiconductor storage device comprising:
one or more memory cells including anti-fuse elements capable of writing data by breaking down a gate insulation film of a MOS transistor with a high voltage;
a sense node having its one end connected to each of the anti-fuse elements;
a sense amplifier comparing a potential of the sense node with a reference potential and amplifying the difference therebetween, the sense amplifier being activated according to a sense-amplifier activation signal;
an initialization circuit initializing the potential of the sense node according to an initialization signal;
a control circuit outputting the initialization signal at a predetermined timing after input of an external signal input from the outside and outputting a first activation signal to activate the sense amplifier at a predetermined timing after input of the external signal; and
a switching circuit outputting the first activation signal as the sense-amplifier activation signal when a normal data read operation is performed, and outputting an inverted version of the external signal as the sense-amplifier activation signal when a test execution is instructed for the one or more memory cells before the gate insulation film is broken down.
2. The non-volatile semiconductor storage device according to claim 1 , wherein
the plurality of memory cells are arranged in parallel.
3. The non-volatile semiconductor storage device according to claim 1 , wherein
the plurality of memory cells are arranged in a grid configuration.
4. The non-volatile semiconductor storage device according to claim 1 , wherein the control circuit comprising:
a first delay circuit outputting a first delayed signal, the first delayed signal corresponding to the external signal delayed at a first timing;
a first AND circuit generating the initialization signal based on an inverted version of the first delayed signal and the external signal;
a second delay circuit generating a second delayed signal, the second delayed signal corresponding to the external signal delayed at a second timing; and
a second AND circuit generating the first activation signal based on the second delayed signal and the external signal.
5. The non-volatile semiconductor storage device according to claim 1 comprising an input/output latch circuit for latching a signal based on a clock signal, wherein
the switching circuit controls a pulse width of the inverted version of the external signal based on the clock signal.
6. The non-volatile semiconductor storage device according to claim 1 comprising a write transistor having its one end connected to the sense node and the other end connected to ground, wherein
the initialization circuit has its one end connected to the sense node and the other end connected to ground.
7. The non-volatile semiconductor storage device according to claim 6 , wherein
the write transistor and the initialization circuit are brought into off states in advance, a write voltage is boosted that is applied to one end of each of the anti-fuse elements when a data write operation is performed, and then the write transistor is brought into an on state.
8. The non-volatile semiconductor storage device according to claim 1 , wherein
when a data read operation is performed, and when a test execution is instructed for the one or more memory cells before the gate insulation film is broken down, a read voltage is applied to one end of each of the anti-fuse elements, and then the sense node is initialized at the initialization circuit.
9. The non-volatile semiconductor storage device according to claim 2 , wherein the control circuit comprising:
a first delay circuit outputting a first delayed signal, the first delayed signal corresponding to the external signal delayed at a first timing;
a first AND circuit generating the initialization signal based on an inverted version of the first delayed signal and the external signal;
a second delay circuit generating a second delayed signal, the second delayed signal corresponding to the external signal delayed at a second timing; and
a second AND circuit generating the first activation signal based on the second delayed signal and the external signal.
10. The non-volatile semiconductor storage device according to claim 2 comprising an input/output latch circuit for latching a signal based on a clock signal, wherein
the switching circuit controls a pulse width of the inverted version of the external signal based on the clock signal.
11. The non-volatile semiconductor storage device according to claim 2 comprising a write transistor having its one end connected to the sense node and the other end connected to ground, wherein
the initialization circuit has its one end connected to the sense node and the other end connected to ground.
12. The non-volatile semiconductor storage device according to claim 11 , wherein
the write transistor and the initialization circuit are brought into off states in advance, a write voltage is boosted that is applied to one end of each of the anti-fuse elements when a data write operation is performed, and then the write transistor is brought into an on state.
13. The non-volatile semiconductor storage device according to claim 2 , wherein
when a data read operation is performed, and when a test execution is instructed for the one or more memory cells before the gate insulation film is broken down, a read voltage is applied to one end of each of the anti-fuse elements, and then the sense node is initialized at the initialization circuit.
14. The non-volatile semiconductor storage device according to claim 3 , wherein the control circuit comprising:
a first delay circuit outputting a first delayed signal, the first delayed signal corresponding to the external signal delayed at a first timing;
a first AND circuit generating the initialization signal based on an inverted version of the first delayed signal and the external signal;
a second delay circuit generating a second delayed signal, the second delayed signal corresponding to the external signal delayed at a second timing; and
a second AND circuit generating the first activation signal based on the second delayed signal and the external signal.
15. The non-volatile semiconductor storage device according to claim 3 comprising an input/output latch circuit for latching a signal based on a clock signal, wherein
the switching circuit controls a pulse width of the inverted version of the external signal based on the clock signal.
16. The non-volatile semiconductor storage device according to claim 3 comprising:
a plurality of word lines;
a row selection decoder, connected to one end of each of the plurality of word lines, selectively activating any one of the plurality of word lines;
a plurality of bit lines connected to one ends of the sense amplifier and the initialization circuit; and
a selection gate transistor having its gate terminal connected to each of the plurality of word lines, its drain terminal connected to the sense node, and its source terminal connected to each of the bit lines.
17. The non-volatile semiconductor storage device according to claim 16 comprising a write transistor having its one end connected to each of the bit lines and the other end connected to ground, wherein
the initialization circuit has its one end connected to the sense node and the other end connected to ground.
18. The non-volatile semiconductor storage device according to claim 17 , wherein
the write transistor and the initialization circuit are brought into off states in advance, a write voltage is boosted that is applied to one end of each of the anti-fuse elements when a data write operation is performed, and then the write transistor is brought into an on state.
19. The non-volatile semiconductor storage device according to claim 3 , wherein
when a data read operation is performed, and when a test execution is instructed for the one or more memory cells before the gate insulation film is broken down, a read voltage is applied to one end of each of the anti-fuse elements, and then the sense node is initialized at the initialization circuit.