Phase-Locked Loop with Adaptive Performance
A phase-locked loop capable of being dynamically configured to optimize phase-noise performance during different modes of operation. The phase-locked loop may include a switchable charge pump, loop filter and voltage-controlled oscillator having auxiliary circuit components that may be switched in and out to achieve calibration settings for optimizing phase-noise performance for different modes of operation, while minimizing unnecessary power consumption, and without disturbing the stability of the phase-locked loop.
1 . A method of optimizing the performance of a phase-locked loop for use in a first and second mode of operation, the method comprising the steps of:
altering characteristics of alterable circuit components of said phase-locked loop to achieve a first calibration setting for optimizing said performance of said phase-locked loop for said first mode of operation; and
altering said characteristics of said alterable circuit components of said phase-locked loop to achieve a second calibration setting for optimizing said performance of said phase-locked loop for said second mode of operation.
2 . The method of claim 1 wherein said performance being optimized comprises the phase-noise performance of said phase-locked loop.
3 . The method of claim 1 wherein said step of altering characteristics comprises switching in and out auxiliary circuit elements in said alterable circuit components.
4 . The method of claim 2 wherein said step of altering characteristics further comprises altering the dBc level of the phase noise of said phase-locked loop without substantially altering the frequency characteristics of the passband or cutoff frequency of said phase noise.
5 . The method of claim 3 wherein said auxiliary circuit elements comprise elements of a charge pump and a loop filter.
6 . The method of claim 3 wherein said auxiliary circuit elements comprise elements of a charge pump and a voltage-controlled oscillator.
7 . The method of claim 3 wherein said auxiliary circuit elements comprise elements of a loop filter and a voltage-controlled oscillator.
8 . The method of claim 3 wherein said auxiliary circuit elements comprise elements of a charge pump, a loop filter and a voltage-controlled oscillator.
9 . A transceiver for use in a first and second mode of operation, comprising:
a frequency synthesizer including a phase-locked loop;
means for altering characteristics of alterable circuit components in said phase-locked loop to achieve a first calibration setting for optimizing performance of said phase-locked loop for said first mode of operation; and
means for altering said characteristics of said alterable circuit components in said phase-locked loop to achieve a second calibration setting for optimizing performance of said phase-locked loop for said second mode of operation.
10 . The transceiver of claim 9 wherein said performance being optimized comprises the phase noise characteristics of said phase-locked loop.
11 . The transceiver of claim 9 wherein said means for altering characteristics includes means for switching in and out auxiliary circuit elements.
12 . The transceiver of claim 10 wherein said means for altering parameters further comprises means for altering the dBc level of the phase noise of said phase-locked loop without substantially altering the frequency characteristics of the passband or cutoff frequency of said phase noise.
13 . The transceiver of claim 11 wherein said auxiliary circuit elements comprise elements of a charge pump and a loop filter.
14 . The transceiver of claim 11 wherein said auxiliary circuit elements comprise elements of a charge pump and a voltage-controlled oscillator.
15 . The transceiver of claim 11 wherein said auxiliary circuit elements comprise elements of a loop filter and a voltage-controlled oscillator.
16 . The transceiver of claim 11 wherein said auxiliary circuit elements comprise elements of a charge pump, a loop filter and a voltage-controlled oscillator.
17 . A communications terminal, comprising:
a transceiver having a frequency synthesizer including a phase-locked loop with a plurality of switchable circuit components including auxiliary circuit elements;
a plurality of switches configured to switch said auxiliary circuit elements in and out of said switchable circuit components; and
a calibration circuit (a) for operating said switches prior to a transmit mode to achieve a first calibration setting for optimizing phase-noise performance of said phase-locked loop for said transmit mode; and (b) for operating said switches prior to a receive mode to achieve a second calibration setting for optimizing phase-noise performance of said phase-locked loop for said receive mode.
18 . The communications terminal of claim 17 wherein said first and second calibration settings are selected such that the phase noise of said phase-locked loop is moved with respect to dBc without substantially affecting the frequency position of the passband or cutoff frequency of said phase noise.
19 . The communications terminal of claim 17 wherein said switchable circuit components comprise a charge pump and a loop filter.
20 . The communications terminal of claim 17 wherein said switchable circuit components comprise a charge pump and a voltage-controlled oscillator.
21 . The communications terminal of claim 17 wherein said switchable circuit components comprise a loop filter and a voltage-controlled oscillator.
22 . The communications terminal of claim 17 wherein said switchable circuit components comprise a charge pump, a loop filter and a voltage-controlled oscillator.