LIQUID CRYSTAL DISPLAY AND METHOD THEREOF
A liquid crystal display (“LCD”) includes a gate line, a data line intersecting the gate line, a pixel including first and second sub-pixels connected to the gate line and the data line, and a coupling capacitor coupled between the first and the second sub-pixels. The first sub-pixel includes a first liquid crystal (“LC”) capacitor and a first thin film transistor (“TFT”). The second sub-pixel includes a second LC capacitor and a second TFT. The first and second TFTs respectively include a gate electrode, a source electrode, and a drain electrode. The gate electrodes of the first and second TFTs are connected to the gate line, the source electrodes of the first and second TFTs are connected to the data line, and the coupling capacitor includes the sub-pixel electrode of the second sub-pixel and the drain electrode of the second TFT as two terminals.
1 . A liquid crystal display comprising:
a gate line;
a data line intersecting the gate line; and
a pixel including a first sub-pixel and a second sub-pixel connected to the gate line and the data line;
wherein the first sub-pixel comprises a first liquid crystal capacitor comprising a first sub-pixel electrode, and a first thin film transistor,
the second sub-pixel comprises a second liquid crystal capacitor comprising a second sub-pixel electrode, a coupling capacitor and a second thin film transistor,
the first and second thin film transistors respectively include a gate electrode, a source electrode, and a drain electrode, the gate electrodes of the first and second thin film transistors are connected to the gate line, and the source electrodes of the first and second thin film transistors are connected to the data line, and
the coupling capacitor comprises the sub-pixel electrode and a coupling electrode connected to the drain electrode of the second thin film transistor as two terminals.
2 . The liquid crystal display of claim 1 , wherein
when the first and second thin film transistors are turned off, a voltage of the first sub-pixel electrode and a voltage of the second sub-pixel electrode drop by a same amount.
3 . The liquid crystal display of claim 2 , wherein
the gate electrodes of the first and second thin film transistors are connected to each other.
4 . The liquid crystal display of claim 3 , wherein
the source electrodes of the first and second thin film transistors are connected to each other.
5 . The liquid crystal display of claim 4 , wherein the gate electrodes protrude from the gate line and the source electrodes protrude from the data line, and a shared semiconductor island is formed between the gate electrodes and the source electrodes.
6 . The liquid crystal display of claim 1 , wherein
the first sub-pixel electrode is connected to the drain electrode of the first thin film transistor.
7 . The liquid crystal display of claim 6 , wherein
the second sub-pixel electrode is coupled with the drain electrode of the second thin film transistor.
8 . The liquid crystal display of claim 7 , wherein
a voltage of the first sub-pixel electrode is different from a voltage of the second sub-pixel electrode.
9 . The liquid crystal display of claim 8 , wherein
the voltage of the first sub-pixel electrode is higher than the voltage of the second sub-pixel electrode.
10 . The liquid crystal display of claim 8 , wherein
an area of the first sub-pixel electrode is different from an area of the second sub-pixel electrode.
11 . The liquid crystal display of claim 1 , wherein
the first sub-pixel further comprises a first storage capacitor and the second sub-pixel further comprises a second storage capacitor.
12 . A liquid crystal display comprising:
a pixel electrode including a first sub-pixel electrode and a second sub-pixel electrode separated from the first sub-pixel electrode;
a first thin film transistor connected to the first sub-pixel electrode;
a second thin film transistor connected to a coupling electrode overlapped by the
second sub-pixel electrodes; and
a storage electrode overlapped by the first and second sub-pixel electrodes;
wherein the second thin film transistor includes a drain electrode and
the coupling electrode is connected to the drain electrode of the second thin film transistor.
13 . The liquid crystal display of claim 12 , further comprising
a first signal line connected to the first and second thin film transistors, and
a second signal line connected to the first and second thin film transistors and intersecting the first signal line.
14 . A method of reducing generation of an image-retension in a liquid crystal display, the liquid crystal display including a pixel comprising a first sub-pixel and a second sub-pixel, the method comprising:
applying first and second sub-pixel electrode voltages to the first and second sub-pixels via a same data line, the second sub-pixel electrode voltage being less than the first sub-pixel electrode voltage;
applying a gate off voltage to first and second liquid crystal capacitors of the first and second sub pixels via a same gate line; and,
substantially equalizing an amount of first and second kickback voltages of the first and second sub-pixels.
15 . The method of claim 14 , wherein substantially equalizing first and second kickback voltages of the first and second sub-pixels includes controlling parasitic capacitances, liquid crystal capacitors, and storage capacitors of the first and second sub-pixels.
16 . The method of claim 14 , wherein
the first sub-pixel comprises the first liquid crystal capacitor comprising a first sub-pixel electrode and a first thin film transistor,
the second sub-pixel comprises the second liquid crystal capacitor comprising a second sub-pixel electrode, a coupling capacitor and a second thin film transistor,
the first and second thin film transistors respectively include a gate electrode, a source electrode, and a drain electrode, the gate electrodes of the first and second thin film transistors are connected to the gate line, and the source electrodes of the first and second thin film transistors are connected to the data line, and
the coupling capacitor comprises the sub-pixel electrode and a coupling electrode connected to the drain electrode of the second thin film transistor as two terminals.
17 . The method of claim 14 , wherein
the first sub-pixel includes a first sub-pixel electrode and a first thin film transistor connected to the first sub-pixel electrode, and the second sub-pixel includes a second sub-pixel electrode separated from the first sub-pixel electrode and a second thin film transistor which comprises a drain electrode, and a coupling electrode is connected to the drain electrode and overlapped the second sub-pixel electrode.