IP Library Granted Patent US 7,916,260
Granted Patent B2
US 7,916,260 · App. 12/033,986 · Granted Mar 29, 2011

Display substrate, method for manufacturing the same and display apparatus having the same

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Quick Facts
Patent No.
US 7,916,260
App. No.
12/033,986
Granted
Mar 29, 2011
Kind
B2
Abstract

A display substrate includes a first metal pattern formed on a substrate and includes a data line to which a pixel voltage is applied, an insulating layer formed on the substrate on which the first metal pattern is formed, an active pattern formed on the insulating layer, a second metal pattern formed on the insulating layer and including a gate line and a storage line, the gate line crossing the data line, a scanning signal applied to the gate line, a protective layer formed on the substrate on which the second metal pattern is formed, and a pixel electrode formed on the protective layer. A method for manufacturing the display substrate, and a display apparatus including the display substrate are further provided.

Claims (49)

1. A display substrate comprising:

a first metal pattern formed on a substrate and including a data line to which a pixel voltage is applied and a gate electrode;

an insulating layer formed on the substrate on which the first metal pattern is formed;

an active pattern formed on the insulating layer;

a second metal pattern formed on the insulating layer and including a gate line and a storage line, the gate line crossing the data line, a scanning signal applied to the gate line;

a protective layer formed on the substrate on which the second metal pattern is formed; and

a pixel electrode formed on the protective layer.

2. The display substrate of claim 1 , wherein the gate electrode is separated from the data line.

3. The display substrate of claim 2 , wherein the second metal pattern further comprises:

a source electrode at least partially overlapping with the gate electrode; and

a drain electrode at least partially overlapping with the gate electrode and electrically connected to the pixel electrode.

4. The display substrate of claim 3 , wherein the active pattern is at least partially formed between the insulating layer and the source and drain electrodes.

5. The display substrate of claim 3 , further comprising:

a first connecting electrode electrically connecting the data line to the source electrode; and

a second connecting electrode electrically connecting the gate line to the gate electrode.

6. The display substrate of claim 5 , wherein the first and second connecting electrodes include a transparent conductive layer.

7. The display substrate of claim 1 , wherein the storage line comprises:

a first portion extending substantially parallel to the gate line; and

a second portion extending from the first portion to overlap with the data line.

8. The display substrate of claim 7 , wherein a width of the second portion is larger than a width of the data line disposed under the second portion.

9. The display substrate of claim 7 , wherein the first and second portions partially overlap with the pixel electrode.

10. The display substrate of claim 9 , wherein an overlapping distance between the second portion and the pixel electrode is between about 2 μm and about 5 μm.

11. The display substrate of claim 7 , wherein the storage line is electrically separated from the gate line.

12. A display apparatus comprising:

a display substrate including:

a first metal pattern formed on a first substrate and including a data line to which a pixel voltage is applied and a gale electrode;

an insulating layer formed on the first substrate on which the first metal pattern is formed;

an active pattern formed on the insulating layer;

a second metal pattern formed on the insulating layer and including a gate line and a storage line, the gate line crossing the data line, and a scanning signal applied to the gate line;

a protective layer formed on the first substrate on which the second metal pattern is formed; and

a pixel electrode formed on the protective layer;

an opposite substrate facing the display substrate; and

a liquid crystal layer disposed between the display substrate and the opposite substrate.

13. The display apparatus of claim 12 , wherein the gate electrode is separated from the data line, and

the second metal pattern further comprises a source electrode at least partially overlapping with the gate electrode, and a drain electrode at least partially overlapping with the gate electrode and electrically connected to the pixel electrode.

14. The display apparatus of claim 13 , wherein the display substrate further comprises:

a first connecting electrode electrically connecting the data line to the source electrode; and

a second connecting electrode electrically connecting the gate line to the gate electrode.

15. The display apparatus of claim 12 , wherein the storage line comprises:

a first portion extending substantially parallel to the gate line; and

a second portion extending from the first portion to overlap with the data line.

16. The display apparatus of claim 15 , wherein a width of the second portion is larger than a width of the data line disposed under the second portion.

17. The display apparatus of claim 15 , wherein the first and second portions partially overlap with the pixel electrode.

18. The display apparatus of claim 17 , wherein an overlapping distance between the second portion and the pixel electrode is between about 2 μm and about 5 μm.

19. The display apparatus of claim 15 , wherein the opposite substrate comprises:

a black matrix formed at a side of each pixel; and

a common electrode formed on a surface of the opposite substrate facing the display substrate.

20. The display apparatus of claim 19 , wherein a width of the black matrix disposed over the data line is smaller than a width of the second portion of the storage line.

21. The display apparatus of claim 20 , wherein a difference between the width of the black matrix disposed over the data line and the width of the second portion of the storage line is between about 4 μm and about 5 μm.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 27, 2012
From: SAMSUNG ELECTRONICS CO., LTD.
To: SAMSUNG DISPLAY CO., LTD.
Reel/Frame 029093/0177 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 20, 2008
From: LEE, BONG-JUN; HUR, MYUNG-KOO; KIM, JONG-OH; SEO, DONG-WUUK; KIM, SUNG-MAN
To: SAMSUNG ELECTRONICS CO., LTD
Reel/Frame 020533/0219 →