Using common mode differential data signals of DDR2 SDRAM for control signal transmission
View Patent ↗A double-data-rate two synchronous dynamic random access (DDR 2 ) memory circuit includes a low-speed input path and a high-speed input path coupled thereto by an input coupling and forming a common input, the common input coupled to a memory core, the memory core having a common output wherein a high-speed output path and a low-speed output path are coupled together by an output coupling and further coupled to the common output of the memory core.
1. A double-data-rate two synchronous dynamic random access (DDR2) memory circuit comprising:
a low-speed input path and a high-speed input path coupled thereto by an input coupling and forming a common input, the common input coupled to a memory core, the memory core having a common output wherein a high-speed output path and a low-speed output path are coupled together by an output coupling and further coupled to the common output of the memory core.
2. The DDR2 memory circuit of claim 1 , wherein the output coupling comprises one of a filter and a tap.
3. The DDR2 memory circuit of claim 2 , wherein the filter comprises a low-pass filter.
4. The DDR2 memory circuit of claim 1 , wherein an operating voltage for the memory circuit is within a range of about 0 volts to about 1.8 volts.