IP Library Granted Patent US 8,110,832
Granted Patent B2
US 8,110,832 · App. 12/034,846 · Granted Feb 7, 2012

Electro-optical substrate, method for designing the same, electro-optical device, and electronic apparatus

Assignee: Seiko Epson Corporation
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Quick Facts
Patent No.
US 8,110,832
App. No.
12/034,846
Granted
Feb 7, 2012
Kind
B2
Abstract

An electro-optical substrate, including: a transparent substrate; a first light-shielding layer arranged on a first surface of the transparent substrate, in at least part of a region surrounding an opening in plan view; a first insulating layer arranged in a position facing the transparent substrate with the first light-shielding layer interposed therebetween, the first insulating layer having a refraction index n and a layer thickness t measured in nanometers, and covering at least part of the first light-shielding layer; a semiconductor layer, arranged in a position facing the transparent substrate, with the first light-shielding layer interposed therebetween, containing part of a thin film transistor, the thin film transistor including a channel region which is, in plan view, positioned within the first light-shielding layer, a corner edge of the first light-shielding layer and a corner edge of the channel region having a distance L c therebetween in nanometers, the distance L c satisfying relational expression 1: nt 2 <244L c ; a gate insulating layer covering the channel region; a gate electrode arranged in a region facing the channel region, with the gate insulating layer being interposed therebetween; a second insulating layer arranged to a position covering at least the gate electrode; and a second light-shielding layer provided in a position facing the semiconductor layer with the second insulating layer interposed therebetween, so as to cover at least the channel region.

Claims (42)

1. An electro-optical substrate, comprising:

a transparent substrate;

a first light-shielding layer arranged on a first surface of the transparent substrate, in at least part of a region surrounding an opening in plan view, the first light-shielding layer having a thickness of 100 to 1,000 nanometers;

a first insulating layer arranged in a position facing the transparent substrate with the first light-shielding layer interposed therebetween, the first insulating layer having a refraction index n and a layer thickness t of less than 285 nanometers, and covering at least part of the first light-shielding layer, the first insulating layer comprising a dense layer and a buffer layer covering the first light-shielding layer;

a semiconductor layer, arranged in a position facing the transparent substrate, with the first light-shielding layer interposed therebetween, containing part of a thin film transistor, the thin film transistor including a channel region which is, in plan view, positioned within the first light-shielding layer, a corner edge of the first light-shielding layer and a corner edge of the channel region having a distance L c therebetween in nanometers, the distance L c being less than 500 nanometers and satisfying relational expression 1:

nt 2 <244 L c

a gate insulating layer covering the channel region;

a gate electrode arranged in a region facing the channel region, with the gate insulating layer being interposed therebetween;

a second insulating layer arranged to a position covering at least the gate electrode; and

a second light-shielding layer provided in a position facing the semiconductor layer with the second insulating layer interposed therebetween, so as to cover at least the channel region, wherein

the dense layer is arranged entirely inside a region covered by the second light-shielding layer so that the dense layer avoids the opening in plan view.

2. The electro-optical substrate according to claim 1 , wherein:

the semiconductor layer includes:

the thin film transistor having a lightly doped drain region;

the distance L c between the corner edge of the first light-shielding layer and the corner edge of the channel region satisfying relational expression 1; and

a distance L l measured in nanometers between the corner edge of the first light-shielding layer and the corner edge of the lightly doped drain region satisfying relational expression 2:

nt 2 <244 L l .

3. An electronic apparatus comprising the electro-optical substrate according to claim 1 .

4. An electronic apparatus comprising the electro-optical device according to claim 3 .

5. The electro-optical substrate according to claim 1 , wherein the buffer layer comprises silicon oxide and the dense layer comprises silicon nitride.

6. The electro-optical substrate according to claim 1 , wherein the dense layer covers at least an upper surface and a side surface of the first light-shielding layer.

7. An electro-optical substrate, comprising:

a transparent substrate;

a first light-shielding layer arranged on a first surface of the transparent substrate, in at least part of a region surrounding an opening in plan view, the first light-shielding layer having a thickness of 100 to 1,000 nanometers;

a first insulating layer arranged in a position facing the transparent substrate with the first light-shielding layer interposed therebetween, the first insulating layer having a refraction index n and a layer thickness t of less than 285 nanometers, and covering at least part of the first light-shielding layer, the first insulating layer comprising a dense layer and a buffer layer covering the first light-shielding layer;

a semiconductor layer, arranged in a position facing the transparent substrate, with the first light-shielding layer interposed therebetween, containing part of a thin film transistor, the thin film transistor including a channel region which is, in plan view, positioned within the first light-shielding layer, a corner edge of the first light-shielding layer having a distance X c in nanometers from a feet of a perpendicular dropped from a corner edge of the channel region to the first light-shielding layer, the distance X c satisfying relational expression 3:

t ( n 2 t 2 −0.3721λ 2 ) 0.5 <0.61λ X c

where λ is the shortest wavelength of light incident to the transparent substrate, λ measured in nanometers;

a gate insulating layer covering the channel region;

a gate electrode arranged in a region facing the channel region, with the gate insulating layer being interposed therebetween;

a second insulating layer arranged to a position covering at least the gate electrode; and

a second light-shielding layer provided in a position facing the semiconductor layer with the second insulating layer interposed therebetween, so as to cover at least the channel region, wherein

the dense layer is arranged entirely inside a region covered by the second light-shielding layer so that the dense layer avoids the opening in plan view.

8. The electro-optical substrate according to claim 7 , wherein:

the semiconductor layer includes:

the thin film transistor having a lightly doped drain region;

the distance L c between the corner edge of the first light-shielding layer and the corner edge of the channel region satisfying relational expression 3; and

a distance X l measured in nanometers between the corner edge of the first light-shielding layer and a feet of a perpendicular dropped from a corner edge of the lightly doped drain region to the first light-shielding layer, the distance X l satisfying relational expression 4:

t ( n 2 t 2 −0.3721λ 2 ) 0.5 <0.61λ X l

where λ is the shortest wavelength of light incident to the transparent substrate, λ measured in nanometers.

9. The electro-optical substrate according to claim 7 , wherein the buffer layer comprises silicon oxide and the dense layer comprises silicon nitride.

10. The electro-optical substrate according to claim 7 , wherein the dense layer covers at least an upper surface and a side surface of the first light-shielding layer.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 28, 2019
From: SEIKO EPSON CORPORATION
To: 138 EAST LCD ADVANCEMENTS LIMITED
Reel/Frame 050197/0212 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 21, 2008
From: HIROSHIMA, YASUSHI
To: SEIKO EPSON CORPORATION
Reel/Frame 020551/0346 →
Priority Claims (2)
JP 2007-041846 · Feb 22, 2007 · national
JP 2008-008805 · Jan 18, 2008 · national
Continuity (1)
Related Publication 20080203396A1 · Aug 28, 2008