Gray code counter and display device therewith
View Patent ↗There is offered a Gray code counter with which a delay time of a critical path is reduced and a fast operation is made possible. A first Gray code bit Q 0 is obtained by outputting an output signal Q 0 o of an RDFF 2 through an RDFF 31 to synchronize with a clock CLK. A second Gray code bit Q 1 is obtained by outputting an output signal Q 1 o of an RDFF 2 through an RDFF 32 to synchronize with the clock CLK. A third Gray code bit Q 2 is obtained by delaying an output signal Q 2 o of an RDFF 4 with a selection circuit 21 and outputting it through an RDFF 33 to synchronize with the clock CLK. A fourth Gray code bit Q 3 is obtained by delaying an output signal Q 3 o of an RDFF 5 with an AND circuit 11 and a selection circuit 22 and outputting it through an RDFF 34 to synchronize with the clock CLK. Higher bits of the Gray code are similarly generated.
1. A Gray code counter that generates a Gray code, comprising:
a divider circuit that halves a frequency of a clock made of an (n−1) th bit of the Gray code that is one bit lower than a n th bit of the Gray code;
a delay circuit that delays an output of the divider circuit based on an (n−2) th bit and lower bits of the Gray code; and
a sequential circuit that holds and delays an output of the delay circuit and outputs the n th bit of the Gray code in response to a clock.
2. The Gray code counter of claim 1 , wherein the delay circuit selects the output of the divider circuit when values of the (n−2) th bit and the lower bits of the Gray code are of a first value and selects an output of the sequential circuit when one of the values of the (n−2) th bit and the lower bits of the Gray code is of a second value.
3. The Gray code counter of claim 1 , wherein the delay circuit comprises a logical product circuit that generates a logical product of (n−2) bits, which are a first bit through the (n−2) th bit, of the Gray code and a selection circuit that selects the output of the divider circuit when a value of the logical product is of a first value and selects an output of the sequential circuit when the value of the logical product is of a second value.
4. A display device comprising a Gray code counter, the Gray code counter comprising:
a divider circuit that halves a frequency of a clock made of an (n−1) th bit of the Gray code that is one bit lower than a n th bit of the Gray code;
a delay circuit that delays an output of the divider circuit based on an (n−2) th bit and lower bits of the Gray code; and
a sequential circuit that holds and delays an output of the delay circuit and outputs the n th bit of the Gray code in response to a clock.
5. The display device of claim 4 , wherein the delay circuit selects the output of the divider circuit when values of the (n−2) th bit and the lower bits of the Gray code are of a first value and selects an output of the sequential circuit when one of the values of the (n−2) th bit and the lower bits of the Gray code is of a second value.
6. The display device of claim 4 , wherein the delay circuit comprises a logical product circuit that generates a logical product of (n−2) bits, which are a first bit through the (n−2) th bit, of the Gray code and a selection circuit that selects the output of the divider circuit when a value of the logical product is of a first value and selects an output of the sequential circuit when the value of the logical product is of a second value.