Power semiconductor device including a double metal contact
View Patent ↗A power semiconductor device that includes a stack of a thin metal layer and a thick metal layer over the active region thereof, and a method for the fabrication thereof.
1. A power semiconductor device comprising:
a semiconductor body including an active region on one surface thereof, said active region including source regions and gate electrodes;
a first metal layer disposed on said one surface and coupled to said source regions;
a gate bus arrangement disposed over said one surface lateral to and spaced from said first metal layer, said gate bus arrangement including a metallic gate bus disposed over a polysilicon gate bus and an insulation body between said polysilicon gate bus and said one surface, wherein said gate bus arrangement is not disposed within a trench, and said gate bus arrangement is disposed entirely above said one surface;
a buffer body disposed over said gate bus arrangement and in a space between said gate bus arrangement and said first metal layer; and
a second metal layer disposed over said first metal layer and extending over and covering said buffer body, a portion of said second metal layer forming a gate pad disposed over said active region and coupled to said metallic gate bus through said buffer body.
2. The power semiconductor device of claim 1 , wherein said first metal layer and said metallic gate bus are less than 2 microns thick.
3. The power semiconductor device of claim 1 , wherein said second metal layer is more then 4 microns thick.
4. The power semiconductor device of claim 1 , wherein said second metal layer is more then 4-20 microns thick.
5. The power semiconductor device of claim 1 , wherein said buffer body is comprised of polyimide.
6. The power semiconductor device of claim 1 , further comprising a hermetic sealant body disposed between said gate bus arrangement and said buffer body.
7. The power semiconductor device of claim 6 , wherein said hermetic sealant body comprises a stack of PSG and silicon nitride.
8. A trench MOSFET comprising:
source regions and gate electrodes within trenches in a semiconductor body;
a drift region and a drain region below said source regions;
a first metal layer disposed on and coupled to said source regions;
a gate bus arrangement disposed lateral to and spaced from said first metal layer, said gate bus arrangement including a metallic gate bus disposed over a polysilicon gate bus and an insulation body between said polysilicon gate bus and a top surface of said semiconductor body, wherein said gate bus arrangement is not disposed within a trench, and said gate bus arrangement is disposed entirely above said top surface;
a buffer disposed over said gate bus arrangement and in a space between said gate bus arrangement and said first metal layer;
a conductive gate pad disposed over said buffer and over an active region of said trench MOSFET, said conductive gate pad coupled to said metallic gate bus through said buffer;
a second metal layer disposed over said first metal layer and extending over and covering said buffer.
9. The trench MOSFET of claim 8 , wherein said second metal layer forms said conductive gate pad.
10. The trench MOSFET of claim 8 , further comprising a hermetic sealant disposed between said gate bus arrangement and said buffer.
11. The trench MOSFET of claim 10 , wherein said hermetic sealant comprises PSG.
12. The trench MOSFET of claim 10 , wherein said hermetic sealant comprises silicon nitride.