Integrated circuit with a subsurface diode
View Patent ↗An integrated circuit includes a first and second diode connected in parallel. The first diode has a first breakdown voltage and has first P type region and first N type region adjacent to each other at the surface of the substrate of a substrate to form a lateral diode. The second diode has a second breakdown voltage less than the first breakdown voltage and has a second P type region and second N type region lateral adjacent to each other in the substrate to form a lateral diode below the surface The first and second N type regions overlap and the first and second P type region being electrically connected whereby the first and second diodes are in parallel.
1. An integrated circuit comprising:
a substrate having a surface;
a first diode having a first breakdown voltage and having first P type region and first N type region adjacent to each other at the surface of the substrate to form a lateral diode;
a second diode having a second breakdown voltage less than the first breakdown voltage and having a second P type region and second N type region lateral adjacent to each other in the substrate to form a lateral diode having a breakdown region below the surface;
the second P and N type regions being retrograde regions extending from the breakdown region of the second diode to adjacent the surface; and
the first and second N type regions overlap and the first and second P type region being electrically connected whereby the first and second diodes are in parallel.
2. The integrated circuit of claim 1 , wherein the second P type and N type regions have a maximum impurity concentration below the surface of the substrate.
3. The integrated circuit of claim 1 , wherein the substrate includes an insulation trench in the surface and the second diode is below the trench.
4. The integrated circuit of claim 1 , wherein the first and second P type regions are spaced in the substrate and are electrically connected by interconnects above the substrate.
5. The integrated circuit of claim 1 , wherein the first and second P type regions overlap to form the electrical connection.
6. The integrated circuit of claim 1 , wherein the first P type region is a body of a lateral field effect transistor and the first N type region is a drain region of the field effect transistor.
7. The integrated circuit of claim 6 , wherein the field effect transistor is an insulated gate field effect transistor.
8. The integrated circuit of claim 1 , wherein the first P and N type regions are the same structure as well regions of CMOS lateral field effect transistors.
9. An integrated circuit comprising:
a substrate having a surface;
a first diode having a first breakdown voltage and having first P type region and first N type region adjacent to each other at the surface of the substrate to form a lateral diode;
a second diode having a second breakdown voltage less than the first breakdown voltage and having a second P type region and second N type region lateral adjacent to each other in the substrate to form a lateral diode below the surface; and
the first and second P type regions being a common P type region abutting the first N type region at the surface and the second N type region below the surface and the first and second N type regions overlap whereby the first and second diodes are in parallel.
10. The integrated circuit of claim 9 , wherein the common P type region and the second N type region have a maximum impurity concentration below the surface of the substrate.