Semiconductor integrated circuit device and fabrication method for the same

1. A semiconductor integrated circuit device comprising:

an integrated active element formed on a semiconductor substrate;

an interlayer insulating film formed on the active element;

at least one or more first metal patterns made of a first metal layer formed in the interlayer insulating film at a position right above the active element, for acting as a first electrode of the active element;

at least one or more second metal patterns made of the first metal layer for acting as a second electrode of the active element;

a first bus made of a second metal layer formed in the interlayer insulating film at a position right above the first metal layer, the first bus being electrically connected with the at least one or more first metal patterns;

a second bus made of the second metal layer, the second bus being electrically connected with the at least one or more second metal patterns;

wherein each of the first bus and the second bus has at least one or more slits; and

at least one or more contact pads provided on the first bus and the second bus,

wherein the contact pad has a probe testing region and a bonding region.

2. The device of claim 1 , wherein the active element is a power transistor.

3. The device of claim 1 , wherein the probe testing regions adjacent to each other and the bonding regions adjacent to each other are respectively placed to be different in the distance from a neighboring chip side.

4. The device of claim 1 , wherein each of the first bus and the second bus has a rectangular shape whose short side is a side parallel to a neighboring chip side and whose long side is a side orthogonal to the chip side.

5. The device of claim 1 , wherein the probe testing region is placed closer to the chip periphery than the bonding region.

6. The device of claim 1 , wherein the bonding region is placed closer to the chip periphery than the probe testing region.

7. The device of claim 1 , wherein the probe testing regions are placed in a staggered array with respect to one direction.

8. A semiconductor integrated circuit device comprising:

an integrated active element formed on a semiconductor substrate;

an interlayer insulating film formed on the active element;

at least one or more first metal patterns made of a first metal layer formed in the interlayer insulating film at a position right above the active element, for acting as a first electrode of the active element;

at least one or more second metal patterns made of the first metal layer for acting as a second electrode of the active element;

at least one or more first buses made of a second metal layer formed in the interlayer insulating film at a position right above the first metal layer, the first bus being electrically connected with a corresponding first metal pattern among the at least one or more first metal patterns;

at least one or more second buses made of the second metal layer, the second bus being electrically connected with a corresponding second metal pattern among the at least one or more second metal patterns;

wherein each of the first bus and the second bus has at least one or more slits;

at least one or more contact pads for probe testing provided for each of the first bus and the second bus, the contact pad for probe testing including a probe testing region; and

at least one or more contact pads for bonding provided for each of the first bus and the second bus, the contact pad for bonding including a bonding region.

9. The device of claim 8 , wherein the contact pad for probe testing is placed adjacent to the contact pad for bonding.

10. The device of claim 8 , wherein the contact pad for probe testing is drawn out with a lead and positioned outside each of the first bus and the second bus.

11. The device of claim 8 , wherein the active element is a power transistor.

12. The device of claim 8 , wherein the probe testing regions adjacent to each other and the bonding regions adjacent to each other are respectively placed to be different in the distance from a neighboring chip side.

13. The device of claim 8 , wherein each of the first bus and the second bus has a rectangular shape whose short side is a side parallel to a neighboring chip side and whose long side is a side orthogonal to the chip side.

14. The device of claim 8 , wherein the probe testing region is placed closer to the chip periphery than the bonding region.

15. The device of claim 8 , wherein the bonding region is placed closer to the chip periphery than the probe testing region.

16. The device of claim 8 , wherein the probe testing regions are placed in a staggered array with respect to one direction.