Phase detector utilizing analog-to-digital converter components
View Patent ↗Methods and systems are provided for an improved phase detector utilizing analog-to-digital converter (ADC) components. In an embodiment, the method includes from an ADC having a sampling clock signal that determines sampling instants, obtaining a first comparison value between an analog signal and a first threshold voltage at a first sampling instant, and obtaining a second comparison value between the analog signal and a second threshold voltage at a second sampling instant. The method further includes, from a supplemental circuit, obtaining a third comparison value between the analog signal and a third threshold voltage at a third sampling instant between the first and second sampling instants. The method further includes processing the first, second, and third comparison values to determine a phase relationship between the analog signal and the sampling clock.
1. A method comprising:
from an analog-to-digital converter having a sampling clock signal that determines sampling instants, obtaining a first comparison value between an analog signal and a first threshold voltage at a first sampling instant, and obtaining a second comparison value between the analog signal and a second threshold voltage at a second sampling instant;
from a supplemental circuit, obtaining a third comparison value between the analog signal and a third threshold voltage at a third sampling instant between the first and second sampling instants; and
processing the first, second, and third comparison values to determine a phase relationship between the analog signal and the sampling clock;
wherein processing the first, second, and third comparison values comprises verifying that the first and second comparison values indicate a voltage transition.
2. The method of claim 1 , wherein the first, second, and third threshold voltages are equal to one another.
3. The method of claim 1 , wherein the first and third threshold voltages are equal to each other, or the second and third threshold voltages are equal to each other, or the first and second threshold voltages are equal to each other.
4. The method of claim 1 , wherein the first, second, and third threshold voltages are different from one another.
5. The method of claim 1 , wherein the analog-to-digital converter comprises a plurality of comparators that each compares an analog signal to a respective threshold voltage, wherein the respective threshold voltages corresponding to the plurality of comparators cooperatively define a voltage range, and wherein the first, second, and third threshold voltages are each approximately at a middle amplitude in the voltage range.
6. The method of claim 1 , wherein a transition point is the time at which the analog signal crosses the third threshold voltage, and wherein processing the first, second, and third comparison values further comprises determining whether the third sampling instant is before or after the transition point.
7. The method of claim 6 , further comprising:
advancing the sampling clock when the third sampling instant is after the transition point; and
retarding the sampling clock when the third sampling instant is before the transition point.
8. The method of claim 1 , wherein the third sampling instant is at a midpoint between the first and second sampling instants.
9. The method of claim 1 , wherein processing the first, second, and third comparison values comprises providing the first, second, and third comparison values to first and second XOR gates.
10. The method of claim 1 , wherein the analog-to-digital converter comprises a plurality of buffers, and wherein obtaining the first and second comparison values comprises obtaining the first and second comparison values from first and second buffers of the plurality of buffers.
11. The method of claim 1 , wherein the analog-to-digital converter comprises a plurality of comparators, and wherein obtaining the first and second comparison values comprises obtaining the first and second comparison values from comparison values generated by one of the comparators of the plurality of comparators.
12. A system comprising:
an analog-to-digital converter having (i) a sampling clock to determine sampling instants, and (ii) a plurality of comparators, wherein a given comparator in the plurality of comparators generates a first plurality of comparison values by comparing the analog signal to a first and second threshold voltages;
a second buffer connected to the given comparator, wherein the second buffer stores a second comparison value generated by the given comparator at a second sampling instant;
a first buffer connected to the second buffer, wherein the first buffer stores a first comparison value generated by the given comparator at a first sampling instant;
a supplemental comparator that generates a second plurality of comparison values by comparing the analog signal to a third threshold voltage;
a supplemental buffer connected to the supplemental comparator, wherein the supplemental buffer stores a third comparison value generated by the supplemental comparator at a third sampling instant between the first and second sampling instants; and
phase detection logic that processes the first, second, and third comparison values to determine a phase relationship between the analog signal and sampling clock.
13. The system of claim 12 , wherein the analog-to-digital converter includes at least one of the first and second buffers.
14. The system of claim 12 , wherein the first, second, and third threshold voltages are equal to one another.
15. The method of claim 12 , wherein the first and third threshold voltages are equal to each other, or the second and third threshold voltages are equal to each other, or the first and second threshold voltages are equal to each other.
16. The method of claim 12 , wherein the first, second, and third threshold voltages are different from one another.
17. The system of claim 12 , wherein the third sampling instant is at a midpoint between the first and second sampling instants.
18. The system of claim 12 , wherein the analog-to-digital converter is a flash analog-to-digital converter that generates a thermometer code having a plurality of bit slots, wherein the first comparison value is a first bit from a given bit slot at the first sampling instant, and wherein the second comparison value is a second bit from the said bit slot at the second sampling instant.
19. The system of claim 12 , further comprising a supplemental sample clock coupled to the supplemental buffer.
20. The system of claim 12 , wherein each of the plurality of comparators compares the analog signal to a respective threshold voltage, wherein the respective threshold voltages corresponding to the plurality of comparators cooperatively define a voltage range, and wherein the first and second threshold voltages are each approximately at a middle voltage in the voltage range.
21. The system of claim 12 , wherein the phase detection logic comprises first and second XOR gates.
22. The system of claim 12 , wherein a transition point is the time at which the analog signal crosses the third threshold voltage, wherein the phase detection logic is configured to
verify that the first and second comparison values indicate a voltage transition; and
determine whether the third sampling instant is before or after the transition point.
23. The system of claim 22 , further comprising phase-correction circuitry configured to:
advance the sampling clock when the third sampling instant is after the transition point; and
retard the sampling clock when the third sampling instant is before the transition point.