Semiconductor integrated circuit
View Patent ↗A semiconductor integrated circuit includes: a memory cell array including a plurality of SRAM memory cells; a characteristic measuring circuit including a plurality of transistor circuits connected in parallel; and a first terminal. The plurality of transistor circuits each include a first transistor configured in the same manner as one of transistors included in one of the SRAM memory cells. The first transistor is connected so as to control current between the first terminal and a node at a reference potential according to a voltage supplied to a gate of the first transistor.
1. A semiconductor integrated circuit comprising:
a memory cell array including a plurality of SRAM (static random-access memory) memory cells;
a characteristic measuring circuit including a plurality of transistor circuits connected in parallel; and
a first terminal,
wherein the plurality of transistor circuits each include a first transistor configured in the same manner as one of transistors included in one of the SRAM memory cells;
the first transistor is connected so as to control current between the first terminal and a node at a reference potential according to a voltage supplied to a gate of the first transistor; and
the gate of the first transistor is connected with a drain or a source thereof.
2. The circuit of claim 1 , wherein the first transistor is configured in the same manner as one of an access transistor and a drive transistor included in the one of the SRAM memory cells.
3. The circuit of claim 1 further comprising a second terminal, wherein the gate of the first transistor is connected with the second terminal.
4. The circuit of claim 1 , wherein the plurality of transistor circuits each further include a second transistor which is configured in the same manner as another one of the transistors included in the one of the SRAM memory cells and which is connected in series with the first transistor; and
the second transistor controls the current between the first terminal and the node at the reference potential according to a voltage supplied to a gate of the second transistor.
5. The circuit of claim 4 , wherein the first and second transistors are configured in the same manner as an access transistor and a drive transistor, respectively, included in the one of the SRAM memory cells.
6. The circuit of claim 4 , wherein the gate of the first transistor is connected with a drain thereof; and
the gate of the second transistor is connected with a drain thereof.
7. The circuit of claim 4 , wherein the gates of the first and second transistors are connected with a drain of the first transistor.
8. The circuit of claim 4 , wherein the reference potential is supplied to the gates of the first and second transistors.
9. The circuit of claim 4 further comprising a second terminal,
wherein the gates of the first and second transistors are connected with the second terminal.
10. The circuit of claim 1 , wherein some of the plurality of transistor circuits belong to a first circuit block, others of the plurality of transistor circuits belong to a second circuit block, and a direction in which the transistor circuits belonging to the first circuit block are disposed and a direction in which the transistor circuits belonging to the second circuit block are disposed differ from each other by about 90 degrees.
11. The circuit of claim 1 comprising a plurality of said characteristic measuring circuits each used for one of different types of transistors having different threshold voltages,
wherein the plurality of SRAM memory cells are formed of the different types of transistors; and
the plurality of characteristic measuring circuits each include, as the first transistors, transistors that are of a type corresponding to that characteristic measuring circuit.