IP Library Granted Patent US 7,777,305
Granted Patent B2
US 7,777,305 · App. 12/041,825 · Granted Aug 17, 2010

Nitride semiconductor device and manufacturing method thereof

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Quick Facts
Patent No.
US 7,777,305
App. No.
12/041,825
Granted
Aug 17, 2010
Kind
B2
Abstract

It is an object of the present invention to provide a nitride semiconductor device with low parasitic resistance by lowering barrier height to reduce contact resistance at an interface of semiconductor and metal. The nitride semiconductor device includes a GaN layer, a device isolation layer, an ohmic electrode, an n-type Al 0.25 Ga 0.75 N layer, a sapphire substrate, and a buffer layer. A main surface of the n-type Al 0.25 Ga 0.75 N layer is on (0 0 0 1) plane as a main surface, and concaves are arranged in a checkerboard pattern on the surface. The ohmic electrode contacts the sides of the concaves of the n-type Al 0.25 Ga 0.75 N layer, and the sides of the concaves are on non-polar surfaces such as (1 1 −2 0) plane or (1 −1 0 0) plane.

Claims (17)

1. A nitride semiconductor device comprising:

a nitride semiconductor layer; and

an ohmic electrode in contact with a side in said nitride semiconductor layer,

wherein concave portions and convex portions are formed on a surface of said nitride semiconductor layer, and

wherein the side is a non-polar surface, and the side is a side of each of the concave portions.

2. The nitride semiconductor device according to claim 1 ,

wherein a bottom surface of each of the concave portions is on (0 3 −3 8) plane or on (0 3 −3 16) plane.

3. The nitride semiconductor device according to claim 1 ,

wherein the concave portions are arranged in a checkerboard pattern or a stripe pattern on the surface of said nitride semiconductor layer.

4. The nitride semiconductor device according to claim 1 , further comprising:

an additional semiconductor layer which is in a heterojunction with said nitride semiconductor layer,

wherein concave portions and convex portions are formed on a surface of said nitride semiconductor layer, and

the concave portions are formed to pass through said nitride semiconductor layer and to reach said additional semiconductor layer.

5. The nitride semiconductor layer according to claim 4 ,

wherein the side is on one of (1 1 −2 0) plane, (1 −1 0 0) plane, (0 3 −3 8) plane, and (0 3 −3 16) plane.

6. The nitride semiconductor layer according to claim 1 ,

wherein the side is on one of (1 1 −2 0) plane, (1 −1 0 0) plane, (0 3 −3 8) plane, and (0 3 −3 16) plane.

Assignments (2)
CHANGE OF NAME Recorded Nov 20, 2008
From: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
To: PANASONIC CORPORATION
Reel/Frame 021897/0516 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 6, 2008
From: KURODA, MASAYUKI; UEDA, TETSUZO
To: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
Reel/Frame 021059/0138 →