Memory compression implementation in a multi-node server system with directly attached processor memory
View Patent ↗A method, apparatus and program product enable scalable bandwidth and memory for a system having processor with directly attached memory. Multiple memory expander microchips provide the additional bandwidth and memory while in communication with the processor. Lower latency data may be stored in a memory expander microchip node in the most direct communication with the processor. Memory and bandwidth allocation between may be dynamically adjusted.
1. An apparatus, comprising:
a memory;
a processor directly attached to the memory; and
a plurality of nodes, wherein at least one of the plurality of the nodes is in communication with the processor, and each of the plurality of the nodes comprises:
a node memory;
a memory expander microchip configured to access the node memory; and
a memory channel connecting the memory expander microchip and the node memory.
2. The apparatus of claim 1 , wherein the memory expander microchip is configured to implement operations involving memory compression.
3. The apparatus of claim 1 , wherein the memory expander microchip is configured to implement operations involving multi-way associativity.
4. The apparatus of claim 1 , wherein the memory expander microchip of the at least one node in communication with the processor includes a cache associated with uncompressed data.
5. The apparatus of claim 1 , wherein the at least one node of the plurality of nodes is configured to communicate with another node of the plurality of nodes, and not to communicate with the processor.
6. The apparatus of claim 5 , wherein the at least one node not configured to communicate with the processor includes compressed data.
7. The apparatus of claim 1 , wherein the memory expander microchip includes a cache.
8. The apparatus of claim 1 , wherein the node memory includes at least one of compressed and uncompressed data.
9. The apparatus of claim 1 , wherein the memory expander microchip includes a compression/decompression engine.
10. The apparatus of claim 1 , wherein the node memory channel includes a portion of the memory channel.
11. The apparatus of claim 1 , wherein the memory expander microchip includes at least one of compressed and uncompressed data.
12. The apparatus of claim 1 , wherein the memory expander microchip is configured to implement memory read and write commands initiated by the processor.
13. An apparatus comprising:
a first memory;
a processor directly attached to the first memory and configured to perform a first memory compression operation; and
a node attached to the processor, the node comprising:
a node memory;
a memory expander microchip configured to access the node memory and to perform a second memory compression operation; and
a memory channel connecting the memory expander microchip and the node memory.
14. The nodal circuit of claim 13 , wherein the memory expander microchip implements memory compression.
15. The nodal circuit of claim 13 , wherein the memory expander microchip implements multi-way associativity.
16. A method of managing compressed memory data, comprising:
attaching a first memory directly to a processor;
attaching a node to the processor;
attaching another node to at least one of the processor and the node, wherein each node comprises:
a node memory;
a memory expander microchip configured to access the node memory; and
a memory channel connecting the memory expander microchip and the node memory; and
performing a memory compression operation on data received at the node.
17. A method of managing compressed memory data, comprising:
attaching a first memory directly to a processor;
attaching a node of a plurality of nodes to the processor;
attaching another node of the plurality of nodes to at least one of the processor and the first node, wherein each of the plurality of nodes comprises:
a node memory;
a memory expander microchip configured to access the node memory; and
a memory channel connecting the memory expander microchip and the node memory; and
performing a memory compression operation on data received at the memory expander microchip.
18. The method of claim 17 , wherein implementing the memory access operation further comprises implementing a memory compression operation.
19. The method of claim 17 , wherein implementing the memory access operation further comprises implementing a multi-way associativity operation.
20. The method of claim 17 , wherein implementing the memory access operation further comprises implementing the operation on a cache comprising part of at least one of the node memory and the memory expander microchip.
21. The method of claim 17 further comprising storing frequently used data in the node attached to the processor.
22. The method of claim 17 further comprising storing at least one of compressed and uncompressed data in the node memory.
23. The method of claim 17 further comprising initiating at the processor the implementation of the memory compression operation on the data.
24. The method of claim 17 further comprising dynamically altering an amount of at least one of uncompressed and compressed data in the other node.
25. A program product, comprising:
program code executed to implement a memory compression operation, wherein the program code resides on a node configured to communicate with both a processor having directly attached memory and another node; and
a computer readable medium bearing the program code.