IP Library Granted Patent US 8,164,360
Granted Patent B2
US 8,164,360 · App. 12/042,780 · Granted Apr 24, 2012

Semiconductor output circuit, external output signal generation method, and semiconductor device

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Quick Facts
Patent No.
US 8,164,360
App. No.
12/042,780
Granted
Apr 24, 2012
Kind
B2
Abstract

A semiconductor output circuit, an external output signal generation method and a semiconductor device that suppress variation in an external output signal caused by a decrease in power supply voltage. An output section changes electric potential of an external output signal EB according to a change in electric potential of an internal input signal A from ground to VDD or from VDD to the ground. A differential section outputs an output signal corresponding to the external output signal EB and a predetermined reference signal VREF. The differential section functions as a voltage follower so that the electric potential of the external output signal EB will correspond to the predetermined reference signal VREF. As a result, variation in output voltage VOL at a low voltage side of the external output signal EB is suppressed.

Claims (10)

1. A semiconductor device which is included in a first chip and is coupled via a bus wiring to a second chip, which is different from the first chip, the semiconductor device comprising:

an external output terminal coupled to the bus wiring;

a first transistor having a gate for receiving an internal input signal, a drain coupled to the external output terminal for outputting to the external output terminal an external output signal generated in response to the internal input signal, and a source;

an operation amplifier having one input terminal coupled to the drain of the first transistor, another input terminal for receiving a predetermined reference signal, and an output terminal;

a second transistor having a gate coupled to the output terminal of the operation amplifier, and a drain coupled to the source of the first transistor; and

an inverter that operates with power supply voltage supplied to the first chip, and receives the internal input signal and inverts and outputs the internal input signal to the gate of the first transistor,

wherein the external output signal is outputted via the external output terminal to the second chip which is different from the first chip; and

wherein the internal input signal is a switching signal.

2. The semiconductor device according to claim 1 , wherein the first transistor is a unipolar transistor, and therein the semiconductor device further comprising a reference voltage generation section coupled to the another input terminal of the operational amplifier for generating the predetermined reference signal, wherein the reference voltage generation section includes a transistor a channel type of which is the same as a channel type of the first transistor.

3. The semiconductor device according to claim 1 , wherein the external output signal is transmitted as information to the second chip via the bus wiring.

Assignments (8)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 27, 2015
From: FUJITSU SEMICONDUCTOR LIMITED
To: SOCIONEXT INC.
Reel/Frame 035508/0637 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 27, 2010
From: FUJITSU ELECTRONICS INC.
To: FUJITSU SEMICONDUCTOR LIMITED
Reel/Frame 024901/0114 →
CHANGE OF NAME Recorded Jul 22, 2010
From: FUJITSU MICROELECTRONICS LIMITED
To: FUJITSU SEMICONDUCTOR LIMITED
Reel/Frame 024748/0328 →
CORRECTIVE ASSIGNMENT TO CORRECT THE FIRST ASSIGNEE'S ADDRESS AND ADD THE SECOND ASSIGNEE'S NAME AND ADDRESS OMITTED ON THE CORRECTED NOTICE OF RECORDATION PREVIOUSLY RECORDED ON REEL 021475 FRAME 0518. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT OF ASSIGNOR(S) INTEREST. Recorded Feb 27, 2009
From: MORII, MASAHARU
To: FUJITSU LIMITED; FUJITSU ELECTRONICS INC.
Reel/Frame 022323/0896 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 26, 2009
From: FUJITSU LIMITED
To: FUJITSU MICROELECTRONICS LIMITED
Reel/Frame 022309/0544 →
CORRECTIVE ASSIGNMENT TO CORRECT THE THE ASSIGNEE ADDRESS PREVIOUSLY RECORDED ON REEL 021025 FRAME 0402. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT OF ASSIGNOR'S INTEREST. Recorded Sep 3, 2008
From: MORII, MASAHARU
To: FUJITSU LIMITED
Reel/Frame 021475/0518 →
CORRECTIVE COVER SHEET TO CORRECT NOTICE OF RECORDATION OF ASSIGNMENT DOCUMENT TO CORRECT ASSIGNEE'S ADDRESS, RECORDED ON MARCH 5, 2008 REEL 020604, FRAME 0229. Recorded May 12, 2008
From: MORII, MASAHARU
To: FUJITSU LIMITED; FUJITSU ELECTRONICS INC.
Reel/Frame 021025/0402 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 5, 2008
From: MORII, MASAHARU
To: FUJITSU LIMITED; FUJITSU ELECTRONICS INC.
Reel/Frame 020604/0229 →