IP Library Granted Patent US 8,209,578
Granted Patent B2
US 8,209,578 · App. 12/046,108 · Granted Jun 26, 2012

Systems using low density parity check codes for correcting errors

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Quick Facts
Patent No.
US 8,209,578
App. No.
12/046,108
Granted
Jun 26, 2012
Kind
B2
Abstract

A system corrects errors in a bit stream. The system includes an encoder and a decoder. The encoder encodes the bit stream using a low density parity check code by inserting parity check bits into the bit stream to generate codewords. The decoder decodes the codewords using parity check equations that are based on the low density parity check code. The parity check bits may comprise no more than four percent of the bits in the codewords of the low density parity check code. The low density parity check code can have a minimum separation of at least 7 between any two ones in each row of a parity-check matrix that is based on the low density parity check code. The encoder and the decoder can be defined in hardware using logic circuits that are interconnected to implement a trellis based on the low density parity check code.

Claims (32)

1. A system for correcting errors in a bit stream, the system comprising:

an encoder that encodes the bit stream using a low density parity check code by inserting parity check bits into the bit stream to generate codewords, wherein the parity check bits comprise no more than four percent of the bits in the codewords of the low density parity check code; and

a decoder that decodes the codewords using parity check equations that are based on the low density parity check code.

2. The system defined in claim 1 wherein the system is a hard disk drive, and the bit stream is read from a magnetic disk in the hard disk drive.

3. The system defined in claim 2 wherein the parity check equations do not contain any four cycles.

4. The system defined in claim 2 wherein the low density parity check code has a minimum separation of at least 7 between any two bits in a codeword that are checked by one of the parity check equations to reduce inter-symbol interference between bits checked by the same parity check equation.

5. The system defined in claim 1 wherein the low density parity check code supports a dynamic length for use with multiple sector formats.

6. The system defined in claim 1 wherein the parity check bits are inserted into each of the codewords in pairs, and each of the pairs in a codeword is separated by at least 22 non-parity check bits.

7. A data storage system for correcting errors in a bit stream, the data storage system comprising:

an encoder that encodes the bit stream using a low density parity check code by inserting parity check bits into the bit stream to generate codewords, wherein the bit stream is read from a data storage medium in the data storage system; and

a decoder that decodes the codewords using a parity-check matrix that is based on the low density parity check code, wherein the low density parity check code has a minimum separation of at least 7 bits between any two ones in each row of the parity-check matrix, such that any two bits checked by each parity check equation that is based on a row of the parity-check matrix are separated by at least 7 bits.

8. The data storage system defined in claim 7 wherein the data storage system is a hard disk drive, and the data storage medium is a magnetic disk.

9. The data storage system defined in claim 7 wherein the parity check bits comprise no more than four percent of the bits in the codewords of the low density parity check code.

10. The data storage system defined in claim 7 wherein parity check equations based on the low density parity check code comprise no more than 508 pseudo four cycles.

11. The data storage system defined in claim 7 wherein parity check equations based on the low density parity check code comprise no more than 508 type 1 proximity four cycles.

12. The data storage system defined in claim 7 wherein parity check equations based on the low density parity check code comprise no more than 2370 type 2 proximity four cycles.

13. The data storage system defined in claim 7 wherein the low density parity check code is generated by using number sequence {0, 2, 17, 18, 23, 10, 3, 12, 1, 15, 22, 5, 21, 6, 14, 11, 9, 19, 13, 8, 7, 20, 16, 4, repeat} to form the parity-check matrix.

14. A data storage system for correcting errors in a bit stream generated from a data storage medium, the data storage system comprising:

an encoder that encodes the bit stream using a low density parity check code by inserting parity check bits into the bit stream to generate codewords, wherein the encoder is defined in hardware using first logic circuits that are interconnected to implement a trellis that is based on the low density parity check code; and

a decoder that decodes the codewords using parity check equations that are based on the low density parity check code, wherein the decoder is defined in hardware using second logic circuits that are interconnected to implement a trellis that is based on the low density parity check code, wherein the low density parity check code is generated by using number sequence {0, 2, 17, 18, 23, 10, 3, 12, 1, 15, 22, 5, 21, 6, 14, 11, 9, 19, 13, 8, 7, 20, 16, 4, repeat} to form a matrix.

15. The data storage system defined in claim 14 wherein the first logic circuits comprise first multiplexers and first memory circuits, and the second logic circuits comprise second multiplexers and second memory circuits.

16. The data storage system defined in claim 14 wherein the low density parity check code has a minimum separation of at least 7 between any two bits in a codeword that are checked by one of the parity check equations.

17. The data storage system defined in claim 14 wherein the low density parity check code equals {β0, β1, β2, β3, β4, β5, β6, β7, β8, β9, β10, β11, β12, β13, β14, β15, β16, β17, β18, β19, β20, β21, β22, β23, β24, β25}, and wherein β is the matrix defined by the number sequence {0, 2, 17, 18, 23, 10, 3, 12, 1, 15, 22, 5, 21, 6, 14, 11, 9, 19, 13, 8, 7, 20, 16, 4, repeat}.

18. A data storage device for correcting errors in a bit stream generated from a data storage medium, the data storage device comprising:

an encoder that encodes the bit stream using a low density parity check code by inserting parity check bits into the bit stream to generate codewords; and

a decoder that decodes the codewords using parity check equations that are based on the low density parity check code, wherein at most four percent of the bits in the codewords of the low density parity check code comprise the parity check bits.

19. A data storage system for correcting errors in a bit stream, the data storage system comprising:

an encoder that encodes the bit stream using a low density parity check code by inserting parity check bits into the bit stream to generate codewords, wherein the bit stream is read from a magnetic data storage medium in the data storage system; and

a decoder that decodes the codewords using parity check equations that are based on the low density parity check code, wherein the parity check equations have a maximum of 508 pseudo four cycles,

wherein each of the pseudo four cycles occurs when two of the parity check equations check two sets of bits, and the bits in each of the sets are separated by one bit location in a codeword.

20. The data storage system defined in claim 19 wherein the parity check equations have a maximum of 508 type 1 proximity four cycles.

21. The data storage system defined in claim 19 wherein the parity check equations have a maximum of 2370 type 2 proximity four cycles.

Assignments (7)
PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
RELEASE OF SECURITY INTEREST AT REEL 052915 FRAME 0566 Recorded Feb 8, 2022
From: JPMORGAN CHASE BANK, N.A.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 059127/0001 →
SECURITY INTEREST Recorded Feb 6, 2020
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS AGENT
Reel/Frame 052915/0566 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 6, 2016
From: HGST NETHERLANDS B.V.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 040826/0821 →
CHANGE OF NAME Recorded Oct 25, 2012
From: HITACHI GLOBAL STORAGE TECHNOLOGIES NETHERLANDS B.V.
To: HGST NETHERLANDS B.V.
Reel/Frame 029341/0777 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 11, 2008
From: GALBRAITH, RICHARD LEO; WILSON, BRUCE ALEXANDER; OENNING, TRAVIS ROGER; BLAUM, MARIO; LAKOVIC, KSENIJA; DJURDJEVIC, IVANA
To: HITACHI GLOBAL STORAGE TECHNOLOGIES NETHERLANDS, B.V.
Reel/Frame 020633/0163 →