System and method for translating non-native instructions to native instructions for processing on a host processor
View Patent ↗A system and method for extracting complex, variable length computer instructions from a stream of complex instructions each subdivided into a variable number of instructions bytes, and aligning instruction bytes of individual ones of the complex instructions. The system receives a portion of the stream of complex instructions and extracts a first set of instruction bytes starting with the first instruction bytes, using an extract shifter. The set of instruction bytes are then passed to an align latch where they are aligned and output to a next instruction detector. The next instruction detector determines the end of the first instruction based on said set of instruction bytes. An extract shifter is used to extract and provide the next set of instruction bytes to an align shifter which aligns and outputs the next instruction. The process is then repeated for the remaining instruction bytes in the stream of complex instructions. The isolated complex instructions are decoded into nano-instructions which are processed by a RISC processor core.
1. A microprocessor, comprising:
an instruction store configured to store variable-length complex instruction set computer (CISC) instructions;
an instruction alignment unit configured to provide an aligned CISC instruction, the instruction alignment unit comprising,
an extract shifter configured to output the CISC instruction as instruction bytes,
an align shifter configured to provide aligned instruction bytes,
an immediate data shifter configured to extract immediate data from the instruction bytes, and
a displacement shifter configured to extract displacement data from the instruction bytes;
an instruction decode unit configured to translate the aligned CISC instruction into one or more corresponding reduced instruction set computer (RISC) instructions; and
an instruction execution unit configured to execute the one or more RISC instructions received from the instruction decode unit.
2. The microprocessor of claim 1 , wherein the align shifter is further configured to separate prefixes from the instruction bytes.
3. The microprocessor of claim 1 , wherein the extract shifter is configured to output the CISC instruction as N instruction bytes, wherein N is a positive integer, and
wherein the align shifter is configured to receive 2N instruction bytes and shift up to N instruction bytes per half cycle.
4. The microprocessor of claim 3 , wherein N is equal to eight (8).
5. The microprocessor of claim 1 , wherein the immediate data shifter and the displacement shifter are configured to receive the aligned instruction bytes.
6. The microprocessor of claim 5 , wherein the instruction bytes received by the immediate data shifter and the displacement shifter are delayed by a half cycle to keep the instruction bytes from the extract shifter substantially synchronized with the aligned instruction bytes from the align shifter.
7. A method, comprising:
storing, in an instruction store, a plurality of variable-length complex instruction set computer (CISC) instructions;
aligning, using an instruction alignment unit, a CISC instruction from the instruction store unit to provide an aligned CISC instruction, wherein the aligning includes,
outputting, using an extract shifter, the CISC instruction as instruction bytes,
aligning, using an align shifter, the instruction bytes to provide aligned instruction bytes,
extracting, using an immediate data shifter, immediate data from the instruction bytes, and
extracting, using a displacement shifter, displacement data from the instruction bytes;
translating the aligned CISC instruction into one or more corresponding reduced instruction set computer (RISC) instructions; and
executing the one or more RISC instructions.
8. The method of claim 7 , wherein the aligning the CISC instruction from the instruction store in the instruction alignment unit further comprises:
separating prefixes from the instruction bytes.
9. The method of claim 7 ,
wherein the outputting the CISC instruction as instruction bytes comprises outputting the CISC instruction as N instruction bytes, wherein N is a positive integer, and
wherein the aligning the instruction bytes to provide aligned instruction bytes comprises shifting up to N instructions bytes per half cycle.
10. The method of claim 9 , wherein N is equal to eight (8).
11. The method of claim 9 , further comprising:
transmitting the aligned instruction bytes to the immediate data shifter and the displacement shifter.
12. The method of claim 11 , further comprising:
delaying the instruction bytes transmitted to the immediate data shifter and the displacement shifter by a half cycle to keep the instruction bytes from the extract shifter substantially synchronized with the aligned instruction bytes from the align shifter.
13. A computer system, comprising:
an external memory;
a microprocessor; and
a bus coupled between the external memory and the microprocessor;
wherein the microprocessor includes,
an instruction store configured to store variable-length complex instruction set computer (CISC) instructions;
an instruction alignment unit configured to provide an aligned CISC instruction, the instruction alignment unit comprising,
an extract shifter configured to output the CISC instruction as instruction bytes,
an align shifter configured to provide aligned instruction bytes,
an immediate data shifter configured to extract immediate data from the instruction bytes, and
a displacement shifter configured to extract displacement data from the instruction bytes;
an instruction decode unit configured to translate the aligned CISC instruction into one or more corresponding reduced instruction set computer (RISC) instructions; and
an instruction execution unit configured to execute the one or more RISC instructions received from the instruction decode unit.
14. The computer system of claim 13 , wherein the align shifter is further configured to separate prefixes from the instruction bytes.
15. The computer system of claim 13 ,
wherein the extract shifter is configured to output the CISC instruction as N instruction bytes, wherein N is a positive integer, and
wherein the align shifter is configured to receive 2N instruction bytes and shift up to N instruction bytes per half cycle.
16. The computer system of claim 15 , wherein N is equal to eight (8).
17. The computer system of claim 13 , wherein the immediate data shifter and the displacement shifter are configured to receive the aligned instruction bytes.
18. The computer system of claim 17 , wherein the instruction bytes received by the immediate data shifter and the displacement shifter are delayed by a half cycle to keep the instruction bytes from the extract shifter substantially synchronized with the aligned instruction bytes from the align shifter.