Pattern detection circuitry
View Patent ↗A pattern detection circuit detects a pattern in a received bit stream, for example a repetitive 8-bit silence pattern in a stream of digital audio data. Summing circuitry forms during first alternate time periods a sum of a first sequence comprising a predetermined number of alternate bits in the bit stream; and forms during second alternate time periods an inverse of a sum of a second sequence comprising the predetermined number of alternate bits in the bit stream. It is then determined whether successive sums formed by the summing circuitry are equal.
1. A pattern detection circuit, for detecting a pattern in a received bit stream, comprising:
summing circuitry,
for forming during first alternate time periods a sum of a first sequence comprising a predetermined number of alternate bits in said bit stream; and
for forming during second alternate time periods an inverse of a sum of a second sequence comprising said predetermined number of alternate bits in said bit stream, the second alternate time periods being interleaved with the first alternate time periods, and the second sequence of alternate bits being interleaved with the first sequence of alternate bits; and
comparison circuitry, for determining whether successive sums formed by the summing circuitry are equal.
2. A pattern detection circuit as claimed in claim 1 , further comprising:
a delay line, for receiving each bit in said bit stream, and comprising a plurality of delay elements each for delaying each received bit by one sample period; and
an adder, connected to said delay line, for forming a sum of a current bit from said bit stream and a plurality of bits received an even number of sample periods previously.
3. A pattern detection circuit as claimed in claim 2 , comprising:
an inverter, connected to receive said bit stream, and to invert alternate bits before passing them to said delay line.
4. A pattern detection circuit as claimed in claim 2 , comprising:
a plurality of inverters, connected to receive from said delay line said current bit from said bit stream and said plurality of bits received an even number of sample periods previously, and to invert its received bits during alternate sample periods before passing them to said adder.
5. A pattern detection circuit as claimed in claim 2 , comprising:
an inverter, connected to receive an output from said adder, and to invert alternate received values before passing them to said comparison circuitry.
6. A pattern detection circuit as claimed in claim 1 , wherein said comparison circuitry is adapted to generate an output signal when successive sums formed by the summing circuitry are equal for a predetermined number of sample periods.
7. A pattern detection circuit as claimed in claim 6 , comprising:
a counter, for receiving clock pulses at a frequency determined by the sample period, and forming a count of received clock pulses, and being reset when said comparison circuitry does not generate an output signal, said counter being adapted to generate an output signal when said count value exceeds a threshold value.
8. An audio reproduction system, comprising:
a pattern detection circuit as claimed in claim 1 , adapted for detecting a silence pattern in a received bit stream of audio data; and
means for controlling said system in response to a detection of a silence pattern.
9. An audio reproduction system as claimed in claim 8 , comprising:
a playback device, associated with said pattern detection circuit in a first device; and
a second device comprising at least a loudspeaker,
wherein the first device is able to transmit data to the second device over a wireless link, and
wherein the pattern detection circuit is adapted to control the second device in response to detection of a silence pattern.
10. An audio reproduction system as claimed in claim 8 , wherein the pattern detection circuit is adapted for distinguishing between different silence patterns detected in the received bit stream of audio data.
11. An audio reproduction system as claimed in claim 9 ,
wherein the second device further comprises an amplifier, for supplying an amplified audio signal to the loudspeaker,
wherein the pattern detection circuit is located in the second device, and
wherein the pattern detection circuit is adapted to mute the loudspeaker in response to detection of a silence pattern.
12. An audio reproduction system as claimed in claim 9 , wherein the first device is adapted to insert a predetermined silence pattern into an audio data stream.
13. An audio reproduction system as claimed in claim 12 , wherein the first device is adapted to detect a silence pattern in an audio data stream received from the playback device, and to modify said silence pattern in data transmitted to the second device.
14. A method of detecting repetitive pattern in a received bit stream, the method comprising:
forming during first alternate time periods a sum of a first sequence comprising a predetermined number of alternate bits in said bit stream; and
forming during second alternate time periods an inverse of a sum of a second sequence comprising said predetermined number of alternate bits in said bit stream, the second alternate time periods being interleaved with the first alternate time periods, and the second sequence of alternate bits being interleaved with the first sequence of alternate bits; and
determining whether the sum of the first sequence and the inverse of the sum of the second sequence sums are equal during a plurality of successive sample periods.
15. A method as claimed in claim 14 , further comprising:
receiving each bit in said bit stream;
delaying each received bit by one sample period; and
forming a sum of a current bit from said bit stream and a plurality of bits received an even number of sample periods previously.
16. A method as claimed in claim 14 , further comprising:
inverting alternate bits before the step of delaying the received bits.
17. A method as claimed in claim 14 , further comprising:
inverting said plurality of bits received an even number of sample periods previously before the step of forming said sum.
18. A method as claimed in claim 14 , further comprising:
inverting said sum of the current bit from said bit stream and the plurality of bits received an even number of sample periods previously.
19. A method as claimed in claim 14 , further comprising:
generating an output signal when successive sums are equal for a predetermined number of sample periods.
20. A method as claimed in claim 19 , further comprising:
receiving clock pulses at a frequency determined by the sample period;
forming a count of received clock pulses, said count being reset when successive sums are not equal; and
generating an output signal when said count value exceeds a threshold value.
21. A method as claimed in claim 14 , further comprising:
controlling an audio reproduction system in response to a detection of a silence pattern.
22. A method as claimed in claim 14 , further comprising:
distinguishing between different silence patterns detected in the received bit stream of audio data.
23. A method as claimed in claim 21 , further comprising:
muting a loudspeaker of said audio reproduction system in response to detection of a silence pattern.
24. A method as claimed in claim 21 , further comprising:
inserting a predetermined silence pattern into an audio data stream.
25. A method as claimed in claim 23 , further comprising:
detecting a silence pattern in an audio data stream received from the playback device, and
modifying said silence pattern.
26. An electronic device comprising an audio reproduction system as claimed in claim 8 .
27. A communications device comprising an audio reproduction system as claimed in claim 8 .
28. A computer device comprising an audio reproduction system as claimed in claim 8 .
29. A vehicle entertainment system, comprising an audio reproduction system as claimed in claim 8 .