CHECKING CIRCUIT OF SENDING CONTROL
The object of the invention is to checking the timing easily and in shorter time, and reduce the power consumption without any influence on other circuits functions. The solutions are as follows. By the “1” detecting counter, the “0” detecting counter, and the data validity judging circuit in the checking circuit of transmission control included in the DSRC baseband circuit of the transmission apparatus, it becomes the possible to judge the data validity of the transmission data TX_DI — 0 . Additionally, by the transmission enable counter 23 and the matched transmission-start-timing judging circuit, it becomes possible to judge the transmission-start-timings of the transmission enable signal TXW_N — 0 and the transmission data TX_DI — 0 . Furthermore, by the transmission-end-timing judging circuit, it becomes possible to judge the end timing of each slot type of the transmission data.
1 . A checking circuit for transmission control being characterized by comprising:
a first counting device for detecting the logic levels 1 and 0 in digital transmission signals controlled to be sent or not by a digital transmission control signal, counting the detecting results, and outputting the counting results;
a data validity judging circuit for judging the data validity of said transmission signals and outputting said judging results based on said counting results of said first counting device;
a second counting device for counting number of said transmission control signals and outputting the second counting results;
a matched transmission-start-timing judging circuit for judging whether or not a transmission-start-timing matches said transmission control signal, using said second counting results based on said judging results, and outputting first judging results.
2 . The checking circuit for transmission control according to claim 1 , being characterized by further comprising:
a third counting device for counting bit number of said first counting results in the case where said judging results shows the data validity.
3 . The checking circuit for transmission control according to claim 2 , being characterized by further comprising:
a transmission-end-timing judging circuit for judging whether or not a transmission-end-timing matches said transmission control signal, using said third counting results based on slot type information, and outputting second judging results.
4 . The checking circuit for transmission control according to claim 1 , wherein said matched transmission-start-timing judging circuit judges whether or not said transmission-start-timing of second counting results subtracted by a set value of advance timing matches said transmission control signal, based on said judging results, and outputs said first judging results.
5 . The checking circuit for transmission control according to claim 4 , wherein said matched transmission-start-timing judging circuit includes an adder and a multiplier.
6 . The checking circuit for transmission control according to claim 3 , wherein said transmission-end-timing judging circuit judges whether or not said transmission-end-timing of said third counting results added by a set value of delay timing based on said slot type information matches said transmission control signal, and outputs second judging results.
7 . The checking circuit for transmission control according to claim 6 , wherein said transmission-end-timing judging circuit includes an adder.
8 . The checking circuit for transmission control according to claims 1 , wherein a data mode of said transmission signal is configured to be switchable by a transmission mode selecting signal.
9 . The checking circuit for transmission control according to claims 1 , wherein said digital transmission control signal is a transmission enable signal for enabling data transmission and activating said transmission enable signal makes said transmission data able to be sent.
10 . The checking circuit for transmission control according to claim 1 , wherein said transmission data switched by said transmission mode selecting signal are data modulated by Amplitude ShiftKeying or Quadriphase Phase Keying.