Semiconductor device and manufacturing method thereof
View Patent ↗In a memory cell area of a semiconductor device, first, second, and third inter-layer insulating films respectively cover a cell transistor, a bit wiring line, and a capacitor which are connected to each other. In an adjacent peripheral circuit area, a peripheral-circuit transistor is covered with the first inter-layer insulating film, a first-layer wiring line connected to the peripheral-circuit transistor is provided on the first inter-layer insulating film and covered with the second inter-layer insulating film, and a second-layer wiring line is provided on the third inter-layer insulating film. In the memory cell area, a landing pad is provided on the second inter-layer insulating film and between the capacitor and a contact plug for connecting the capacitor to the cell transistor. An assist wiring line connected to the first-layer wiring line is provided on the main surface of the second inter-layer insulating film, on which the landing pad is provided.
1. A semiconductor device having a memory cell area for storing data and a peripheral circuit area adjacent thereto on a semiconductor substrate, wherein:
in the memory cell area, a cell transistor, a bit wiring line connected to the cell transistor, and a capacitor also connected to the cell transistor are provided in a vertically-layered structure;
a first inter-layer insulating film is provided so as to cover the cell transistor;
a second inter-layer insulating film is provided so as to cover the bit wiring line which is provided in an upper layer with respect to that of the cell transistor;
a third inter-layer insulating film is provided so as to cover the capacitor which is provided in an upper layer with respect to that of the bit wiring line;
in the peripheral circuit area, a peripheral-circuit transistor is provided and is covered with the first inter-layer insulating film;
a first-layer wiring line connected to the peripheral-circuit transistor is provided on a main surface of the first inter-layer insulating film;
the first-layer wiring line is covered with the second inter-layer insulating film;
a second-layer wiring line is provided on a main surface of the third inter-layer insulating film which is formed on the second inter-layer insulating film;
in the memory cell area, a landing pad is provided on a main surface of the second inter-layer insulating film and at a connection part between the capacitor and a contact plug which is formed for connecting the capacitor to the cell transistor provided in a lower layer; and
an assist wiring line connected to the first-layer wiring line is provided on the main surface of the second inter-layer insulating film, on which the landing pad is provided.
2. The semiconductor device in accordance with claim 1 , wherein the assist wiring line is connected to both the first-layer wiring line and the second-layer wiring line.
3. The semiconductor device in accordance with claim 1 , wherein:
the capacitor has a stacked structure including a lower electrode, a capacitance insulating film, and an upper electrode; and
the landing pad is provided between the lower electrode and the contact plug.
4. The semiconductor device in accordance with claim 1 , wherein the assist wiring line provided on the main surface of the second inter-layer insulating film is arranged to extend on both the memory cell area and the peripheral circuit area on the semiconductor substrate.
5. The semiconductor device in accordance with claim 1 , wherein the assist wiring line provided on the main surface of the second inter-layer insulating film is electrically connected to the first-layer wiring line which is formed on the main surface of the first inter-layer insulating film and is positioned above a separating insulating film by which the memory cell area and the peripheral circuit area are separated from each other on the semiconductor substrate.
6. A method of manufacturing a semiconductor device having a memory cell area for storing data and a peripheral circuit area adjacent thereto on a semiconductor substrate, wherein:
in the memory cell area, a cell transistor, a bit wiring line connected to the cell transistor, and a capacitor also connected to the cell transistor are provided in a vertically-layered structure;
a first inter-layer insulating film is provided so as to cover the cell transistor;
a second inter-layer insulating film is provided so as to cover the bit wiring line which is provided in an upper layer with respect to that of the cell transistor;
a third inter-layer insulating film is provided so as to cover the capacitor which is provided in an upper layer with respect to that of the bit wiring line;
in the peripheral circuit area, a peripheral-circuit transistor is provided and is covered with the first inter-layer insulating film;
a first-layer wiring line connected to the peripheral-circuit transistor is provided on a main surface of the first inter-layer insulating film;
the first-layer wiring line is covered with the second inter-layer insulating film;
a second-layer wiring line is provided on a main surface of the third inter-layer insulating film which is formed on the second inter-layer insulating film;
in the memory cell area, a landing pad is provided on a main surface of the second inter-layer insulating film and at a connection part between the capacitor and a contact plug which is formed for connecting the capacitor to the cell transistor provided in a lower layer;
an assist wiring line connected to the first-layer wiring line is provided on the main surface of the second inter-layer insulating film, on which the landing pad is provided;
the method comprises the steps of:
forming the cell transistor and the peripheral-circuit transistor respectively in the memory cell area and the peripheral circuit area on the semiconductor substrate;
forming the first inter-layer insulating film on a main surface of the semiconductor substrate;
forming the second inter-layer insulating film on the main surface of the first inter-layer insulating film;
forming the third inter-layer insulating film on the main surface of the second inter-layer insulating film;
forming the second-layer wiring line on the main surface of the third inter-layer insulating film;
forming the capacitor in the third inter-layer insulating film;
forming the landing pad for electrically connecting the capacitor to the cell transistor on the main surface of the second inter-layer insulating film in the memory cell area; and
forming the assist wiring line for connecting the first-layer wiring line to the second-layer wiring line on the main surface of the second inter-layer insulating film in the peripheral circuit area; and
the step of forming the landing pad and the step of forming the assist wiring line are performed in a single photolithography process.
7. The method in accordance with claim 6 , wherein:
after a preparatory film for forming the third inter-layer insulating film is formed on the second inter-layer insulating film, a deep-hole cylinder is formed through the preparatory film;
after a lower electrode is formed on the inside of the deep-hole cylinder, the preparatory film is removed, and then a capacitance insulating film and an upper electrode are formed;
after the capacitor is formed by patterning, the third inter-layer insulating film is formed so as to cover the capacitor, and then a plug connected to the assist wiring line is formed; and
the second-layer wiring line connected to the plug is formed on the third inter-layer insulating film.