IP Library Granted Patent US 8,609,326
Granted Patent B2
US 8,609,326 · App. 12/047,572 · Granted Dec 17, 2013

Methods for exposure for the purpose of thermal management for imprint lithography processes

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Quick Facts
Patent No.
US 8,609,326
App. No.
12/047,572
Granted
Dec 17, 2013
Kind
B2
Abstract

The present invention is directed to a method that attenuates, if not avoids, heating of a substrate undergoing imprint lithography process and the deleterious effects associated therewith. To that end, the present invention includes a method of patterning a field of a substrate with a polymeric material that solidifies in response to actinic energy in which a sub-portion of the field is exposed sufficient to cure the polymeric material is said sub-portion followed by a blanket exposure of all of the polymeric material associated with the entire field to cure/solidify the same.

Claims (11)

1. A method of patterning a field located on a surface of a substrate with a polymeric material that solidifies in response to actinic radiation using a template having a mold with a patterning surface thereon, the field having dimensions and the patterning surface having dimensions corresponding to the field dimensions, the method comprising:

depositing the polymeric material on the field;

contacting the patterning surface of the mold with deposited polymeric material;

exposing a sub-portion of said field to said actinic radiation to solidify the polymeric material in the sub-portion of said field while maintaining the patterning surface in contact with the polymeric material;

exposing all of said field including said sub-portion, to said actinic radiation, to solidify the remaining polymeric material in the field while maintaining the patterning surface in contact with the polymeric material; and

separating the template from the solidified polymeric material on the field.

2. The method as recited in claim 1 wherein said substrate is a semiconductor wafer and said field is coextensive with an entire area of one side of said substrate.

3. The method as recited in claim 1 wherein said substrate is a semiconductor wafer and said field is a sub-part of an entire area of one side of said substrate.

4. The method as recited in claim 1 wherein said sub-portion has dimensions and wherein said exposing said sub-portion further includes propagating a flux of said actinic radiation along a path, with said flux having a cross-section that is greater in dimensions than said sub-portion dimensions and further including placing a spatial filter in said path to reduce said flux to dimensions commensurate with said sub-portion dimensions.

5. The method as recited in claim 1 wherein said sub-portion has dimensions and wherein said exposing said sub-portion further includes propagating a flux of said actinic radiation along a path, with said flux having a cross-section that is greater in dimensions than said sub-portion dimensions and further including placing a spatial filter in said path to reduce said flux, to dimensions commensurate with said sub-portion dimensions, and wherein said exposing all of said field further indicates removing said spatial filter from said path.

6. The method of claim 1 further including transferring thermal energy, accumulating in said substrate, away from said substrate by placing said substrate in thermal communication with a support.

Assignments (2)
ASSIGNMENT OF SECURITY INTEREST IN PATENTS Recorded Nov 7, 2019
From: JPMORGAN CHASE BANK, N.A.
To: CITIBANK, N.A.
Reel/Frame 050967/0138 →
PATENT SECURITY AGREEMENT Recorded Aug 22, 2019
From: MAGIC LEAP, INC.; MOLECULAR IMPRINTS, INC.; MENTOR ACQUISITION ONE, LLC
To: JP MORGAN CHASE BANK, N.A.
Reel/Frame 050138/0287 →