Thin film transistor, organic light emitting diode display device having the same, flat panel display device, and semiconductor device, and methods of fabricating the same

1. A thin film transistor, comprising:

a substrate;

a semiconductor layer formed of polycrystalline silicon on the substrate, the semiconductor layer having a variation in height of a top surface of 15 nm or less,

wherein all of the grain boundaries of the semiconductor layer extend in a single crystal growth direction;

a gate electrode formed to correspond to a part of the semiconductor layer;

a gate insulating layer to insulate the gate electrode from the semiconductor layer; and

source and drain electrodes connected to the semiconductor layer.

2. The thin film transistor of claim 1 , wherein grain boundaries extend in a direction of current flow in the semiconductor layer.

3. An organic light emitting diode (OLED) display device, comprising:

a substrate;

a semiconductor layer formed of polycrystalline silicon disposed on the substrate, the semiconductor layer having a variation in height of a top surface of 15 nm or less,

wherein all of the grain boundaries of the semiconductor layer-extend in a single crystal growth direction;

a gate electrode formed to correspond to a part of the semiconductor layer;

a gate insulating layer to insulate the semiconductor layer from the gate electrode;

source and drain electrodes connected to the semiconductor layer;

a first electrode connected to one of the source and drain electrodes;

an organic emitting layer disposed on the first electrode; and

a second electrode disposed on the organic emitting layer.

4. The OLED display device of claim 3 , wherein the grain boundaries extend in a direction of current flow in the semiconductor layer.

5. A flat panel display device, comprising:

a substrate having a pixel region and a peripheral region;

a first polycrystalline silicon layer disposed on the substrate in the pixel region, the first polycrystalline silicon layer including metal catalyst particles at a concentration of 10 13 atoms/cm 3 or less;

a second polycrystalline silicon layer disposed on the substrate in the peripheral region, the second polycrystalline silicon layer having a grain boundary disposed in a crystal growth direction and having a variation of height in a top surface of 15 nm or less;

gate electrodes formed to respectively correspond to parts of the first and second polycrystalline silicon layers;

a gate insulating layer to insulate the first and second polycrystalline silicon layers from the gate electrodes; and

source and drain electrodes respectively connected to parts of the first and second polycrystalline silicon layers;

a first electrode connected to one of the source and drain electrodes connected to the first polycrystalline silicon layer in the pixel region; and

an electrode of a display electrically connected to one of the source or drain electrodes.

6. The device of claim 5 , wherein the polycrystalline silicon layer in the pixel region comprises metal catalyst particles at a concentration of 10 9 to 10 13 atoms/cm 3 .

7. A semiconductor device, comprising:

a substrate having a thin film transistor region and a photodiode region;

a first semiconductor layer disposed on the substrate in the thin film transistor region, and the first semiconductor layer having metal catalyst particles at a concentration of 10 13 atoms/cm 3 or less; and

a second semiconductor layer disposed on the substrate in the photodiode region, the second semiconductor layer having a grain boundary disposed in a crystal growth direction and having a variation in height of a top surface of 15 nm or less;

a gate insulating layer, a gate electrode, an interlayer insulating layer formed on the first semiconductor layer, and source and drain electrodes connected to the first semiconductor layer;

an n-type silicon layer, an intrinsic region, and a p-type silicon layer formed on the second semiconductor layer, and interconnections connected to the second semiconductor layer and the p-type silicon layer.

8. The device of claim 7 , wherein the first semiconductor layer comprises metal catalyst particles at a concentration of 10 9 to 10 13 atoms/cm 3 .