Serial communication system
View Patent ↗A serial communication system includes a master processor and a slave processor. A CS signal for requesting a serial communication is output from the master processor, and an OK_INV signal for responding to the CS signal is output from the slave processor. When a CS signal is an active state, the master processor executes a serial communications of a preset number of bits every time that a level of the OK_INV signal is reversed. The slave processor inverts a level of an OK_INV signal in response to the CS signal shifting to the active state. The slave processor changes the level of the OK_INV signal every time that a serial communication of a preset number of bits is completed.
1. A serial communication system comprising:
a master processor which requests a serial communication by making a communication request signal in an active state, and
a slave processor which outputs an answer signal to respond to said communication request signal, wherein
said slave processor includes a preparer which performs a preparation of a partial amount serial communication, and a first reverser which reverses a level of said answer signal every time that said preparation of said partial amount of serial communication is completed by said preparer, and
said master processor includes a communicator which performs the partial amount of serial communication in response to the level of said answer signal is reversed when said communication request signal is in the active state.
2. A serial communication system according to claim 1 , wherein said master processor includes a first determiner which determines whether or not an end condition is satisfied in response to the level of said answer signal is reversed before said partial amount of serial communication is performed, and a setter which sets said communication request signal in a negative state when it is determined that said end condition is satisfied by said first determiner.
3. A serial communication system according to claim 2 , wherein said slave processor further includes a second determiner which determines whether or not said end condition is satisfied every time that said partial amount of serial communication is completed, and an ender which executes end processing when it is determined by said second determiner that said end condition is satisfied.
4. A serial communication system according to claim 3 , wherein said second determiner executes determining processing with reference to a description of data to be transferred by said partial amount of serial communication.
5. A serial communication system according to one of claim 3 or 4 , wherein said slave processor further includes a second reverser which reverses a level of said answer signal in relation to said end processing.
6. A serial communication method executed by a master processor which requests a serial communication by making a communication request signal in an active state, and a slave processor which outputs an answer signal to respond to said communication request signal, including following steps of: a preparing step, executed by said slave processor, of preparing a partial amount of serial communication; a reversing step, executed by said slave processor, of reversing a level of said answer signal every time that said preparation of said partial amount of serial communication is completed in said preparing step, and a communicating step, executed by said master processor, of performing the partial amount of serial communication in response to the level of said answer signal is reversed when said communication request signal is in the active state.