SEMICONDUCTOR INTEGRATED CIRCUIT AND DESIGN METHOD OF SIGNAL TERMINALS ON INPUT/OUTPUT CELL
A semiconductor integrated circuit, including an input/output cell including signal terminals, wherein the signal terminal of the input/output cell is connected to an internal circuit via an interconnect wiring. The signal terminal of the I/O cell includes a plurality of (e.g., four) conductive layers. Each pair of adjacent ones of the plurality of conductive layers are connected together by a via. One of the plurality of conductive layers to which a via of the largest diameter is connected (e.g., the fourth conductive layer) is formed with a width such that only one of the largest-diameter via can be accommodated. Therefore, it is possible to suppress the migration of atoms from the interconnect wiring to the input terminal of the I/O cell, and to suppress the open failure of the via formed on the interconnect wiring.
1 . A semiconductor integrated circuit, comprising:
an I/O cell including one or more signal terminals and being capable of inputting, outputting or inputting/outputting a signal via the signal terminal; and
an interconnect wiring for connecting the signal terminal of the I/O cell to an internal circuit, wherein:
the signal terminal of the I/O cell is formed by a plurality of conductive layers;
adjacent ones of the plurality of conductive layers are connected together by one or more vias; and
a broadest conductive layer, being a broadest one of the plurality of conductive layers, has a width such that only one largest-diameter via having a largest diameter among all the vias can be accommodated.
2 . The semiconductor integrated circuit of claim 1 , wherein the plurality of conductive layers have a same width.
3 . The semiconductor integrated circuit of claim 1 , wherein at least two of the plurality of conductive layers have different widths from each other.
4 . The semiconductor integrated circuit of claim 1 , wherein:
the broadest conductive layer is an uppermost one of the plurality of conductive layers and has a largest thickness among the plurality of conductive layers; and
the largest-diameter via is a via that connects the uppermost conductive layer with another one of the plurality of conductive layers immediately below the uppermost conductive layer.
5 . The semiconductor integrated circuit of claim 1 , wherein a width of the broadest conductive layer is smaller than twice the diameter of the largest-diameter via.
6 . The semiconductor integrated circuit of claim 1 , wherein a width of the broadest conductive layer is larger than the diameter of the largest-diameter via.
7 . The semiconductor integrated circuit of claim 1 , wherein a width of the broadest conductive layer is equal to the diameter of the largest-diameter via.
8 . The semiconductor integrated circuit of claim 1 , wherein a width of the broadest conductive layer is smaller than the diameter of the largest-diameter via.
9 . The semiconductor integrated circuit of claim 1 , wherein for any pair of adjacent ones of the plurality of conductive layers, one or more vias for connecting the adjacent conductive layers together are arranged in a longitudinal direction of the conductive layers.
10 . The semiconductor integrated circuit of claim 1 , wherein with vias other than the largest-diameter via, more than one of such vias are arranged in a width direction of the conductive layer to which the vias are connected.
11 . The semiconductor integrated circuit of claim 3 , wherein one or more of the conductive layers to which the largest-diameter via is not connected are narrow conductive layers, which are narrower than the broadest conductive layer.
12 . The semiconductor integrated circuit of claim 11 , wherein a width of the narrow conductive layer is smaller than twice a diameter of the via connected to the narrow conductive layer.
13 . The semiconductor integrated circuit of claim 11 , wherein a width of the narrow conductive layer is larger than a diameter of the via connected to the narrow conductive layer.
14 . The semiconductor integrated circuit of claim 11 , wherein a width of the narrow conductive layer is equal to a diameter of the via connected to the narrow conductive layer.
15 . The semiconductor integrated circuit of claim 11 , wherein a width of the narrow conductive layer is smaller than a diameter of the via connected to the narrow conductive layer.
16 . A method for designing a signal terminal on an I/O cell, comprising the steps of:
determining a plurality of conductive layers to be used as the signal terminal on the I/O cell;
obtaining a diameter of one of a plurality of vias each for connecting together adjacent ones of the plurality of conductive layers that has a largest diameter; and
setting a width of one of the plurality of conductive layers to which the largest-diameter via is connected to such a width that only one of the largest-diameter via can be accommodated.
17 . The method for designing a signal terminal on an I/O cell of claim 16 , further comprising the steps of:
estimating an amount of current flow between adjacent ones of the plurality of conductive layers;
calculating a number of vias through which the estimated amount of current can be conducted; and
setting a length of the plurality of conductive layers to a length sufficient for covering the calculated number of vias.