IP Library Granted Patent US 7,900,119
Granted Patent B2
US 7,900,119 · App. 12/049,164 · Granted Mar 1, 2011

Interleaving redundancy apparatus and method

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 7,900,119
App. No.
12/049,164
Granted
Mar 1, 2011
Kind
B2
Abstract

One embodiment of the invention relates to a network communication device. The network communication device includes a network interface configured to receive an initial data stream. The network communication device also includes an interleaving redundancy encoder that comprises a memory unit arranged in N columns and D rows. The interleaving redundancy encoder is configured to calculate at least one redundancy byte based on a series of equally spaced, non-consecutive bytes in the initial data stream, where a number of bytes between equally spaced bytes is approximately equal to D−1. Other systems and methods are also disclosed.

Claims (33)

1. A network device, comprising:

a network interface configured to receive an initial data stream;

an interleaving redundancy encoder comprising a memory unit that arranges data in N columns and D rows; the interleaving redundancy encoder configured to calculate at least one redundancy byte based on a series of equally spaced, non-consecutive bytes in the initial data stream, where a number of bytes between the equally spaced bytes is equal to D−1.

2. The network device of claim 1 , further comprising:

a transmitter configured to transmit an output data stream over a transmission medium, where consecutive bytes in the output data stream have an order that corresponds to an order of consecutive bytes in the initial data stream.

3. The network device of claim 2 , where the initial data stream passes from the network interface to the transmitter with approximately zero effective delay.

4. The network device of claim 2 , where the series of bytes and the at least one redundancy byte are associated with a virtual codeword.

5. The network device of claim 4 , where redundancy bytes for several virtual codewords are calculated in parallel.

6. The network device of claim 4 , where the transmitter is configured to transmit a series of symbols over the transmission medium, each symbol framed to correspond to a unique virtual codeword.

7. An interleaving redundancy encoder adapted to facilitate transmission of data over a transmission medium, comprising:

a memory unit having a number of memory cells arranged in a number of rows and a number of columns;

a write controller configured to write payload bytes to the memory unit according to a first pattern, and further configured to write redundancy bytes to the unit according to a second pattern.

8. The interleaving redundancy encoder of claim 7 , where the first pattern comprises writing consecutive payload bytes from an initial data stream into consecutively incremented rows of a first column, and then writing the next consecutive payload bytes of the initial data stream into consecutively incremented rows of the next column.

9. The interleaving redundancy encoder of claim 8 , where the second pattern comprises writing a redundancy byte based on the payload bytes of a row of the memory unit.

10. The interleaving redundancy encoder of claim 7 , further comprising:

a read controller configured to read the payload bytes from the memory unit according to the first pattern.

11. The interleaving redundancy encoder of claim 10 , where the read controller is configured to read the redundancy bytes from the memory unit according to the third pattern.

12. The interleaving redundancy encoder of claim 10 , where the read controller is further configured to read the redundancy bytes from the unit according to a third pattern that differs from the second pattern.

13. An interleaving redundancy encoder adapted to facilitate transmission of data over a transmission medium, comprising:

a memory unit having a number of memory cells arranged in a number of rows and a number of columns;

a first redundancy encoder configured to calculate at least one redundancy byte based on data values in a row of the memory unit;

a second redundancy encoder configured to calculate at least one redundancy byte based on data values in a column of the memory unit.

14. The interleaving redundancy encoder of claim 13 , where the first and second redundancy encoders use different encoding algorithms.

15. The interleaving redundancy encoder of claim 13 , where the first redundancy component uses a first algorithm that provides for error detection and correction, and where the second redundancy component uses a second algorithm that provides for only error detection.

16. The interleaving redundancy encoder of claim 13 , where the first redundancy component uses a Reed-Solomon encoding, and where the second redundancy component uses a cyclic redundancy check.

17. A method of data processing, comprising:

writing an initial data stream to columns and rows of a memory unit according to a first pattern;

using a first redundancy algorithm to calculate at least one redundancy byte based on data values along a row of the memory unit;

using a second redundancy algorithm to calculate at least another redundancy byte based on data values along a column of the memory unit, the second redundancy algorithm differing from the first redundancy algorithm.

18. The method of claim 17 , further comprising:

transmitting an outgoing data stream over a transmission medium, where the output data stream includes the initial data stream with the at least one redundancy byte and the at least another redundancy byte therein, and where consecutive bytes in the output data stream have an order that corresponds to an order of consecutive bytes in the initial data stream.

19. The method of claim 17 , where the first algorithm comprises Reed-Solomon encoding.

20. The method of claim 17 , where the second algorithm comprises a cyclic-redundancy check.

Assignments (10)
SECURITY AGREEMENT Recorded Jul 9, 2021
From: MAXLINEAR, INC.; MAXLINEAR COMMUNICATIONS, LLC; EXAR CORPORATION
To: WELLS FARGO BANK, NATIONAL ASSOCIATION
Reel/Frame 056816/0089 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 27, 2020
From: INTEL CORPORATION
To: MAXLINEAR, INC.
Reel/Frame 053626/0636 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 20, 2020
From: LANTIQ BETEILIGUNGS-GMBH & CO. KG
To: INTEL CORPORATION
Reel/Frame 053259/0678 →
MERGER AND CHANGE OF NAME Recorded Jan 17, 2018
From: LANTIQ DEUTSCHLAND GMBH; LANTIQ BETEILIGUNGS-GMBH & CO. KG
To: LANTIQ BETEILIGUNGS-GMBH & CO. KG
Reel/Frame 045085/0292 →
MERGER Recorded Dec 18, 2017
From: LANTIQ DEUTSCHLAND GMBH
To: LANTIQ BETEILIGUNGS-GMBH & CO. KG
Reel/Frame 044907/0045 →
RELEASE OF SECURITY INTEREST RECORDED AT REEL/FRAME 025413/0340 AND 025406/0677 Recorded Apr 17, 2015
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: LANTIQ BETEILIGUNGS-GMBH & CO. KG
Reel/Frame 035453/0712 →
GRANT OF SECURITY INTEREST IN U.S. PATENTS Recorded Nov 29, 2010
From: LANTIQ DEUTSCHLAND GMBH
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 025406/0677 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 15, 2010
From: INFINEON TECHNOLOGIES WIRELESS SOLUTIONS GMBH
To: LANTIQ DEUTSCHLAND GMBH
Reel/Frame 024529/0656 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 3, 2010
From: INFINEON TECHNOLOGIES AG
To: INFINEON TECHNOLOGIES WIRELESS SOLUTIONS GMBH
Reel/Frame 024483/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 17, 2008
From: HEISE, BERND
To: INFINEON TECHNOLOGIES AG
Reel/Frame 020662/0903 →