IP Library Granted Patent US 8,040,299
Granted Patent B2
US 8,040,299 · App. 12/049,747 · Granted Oct 18, 2011

Active matrix of an organic light-emitting diode display screen

Assignee: Thales
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Quick Facts
Patent No.
US 8,040,299
App. No.
12/049,747
Granted
Oct 18, 2011
Kind
B2
Abstract

An active matrix for an organic light-emitting diode display screen, including: pixels arranged in rows and in columns, each pixel including, a pixel electrode capable of accommodating an organic light-emitting diode on the surface, and first and second current drivers connected to said pixel electrode, wherein the first and second current drivers each include a current control transistor connected between a supply voltage Vdd and said pixel electrode and at least a first switching transistor that controls a gate of said current control transistor.

Claims (24)

1. An active matrix for an organic light-emitting diode display screen, comprising:

pixels arranged in rows and in columns, each pixel including,

a pixel electrode capable of accommodating an organic light-emitting diode on the surface, and

first and second current drivers connected to said pixel electrode, wherein the first and second current drivers each include,

a current control transistor connected between a supply voltage Vdd and said pixel electrode, and

at least a first switching transistor that controls a gate of said current control transistor,

wherein said first switching transistor is connected between a column data line of the matrix and the gate of said current control transistor,

a gate of the first switching transistor is connected to a row select line of the matrix, and

source or drain electrodes of the first switching transistor and the current control transistor, and the pixel electrodes are disposed at a source-drain metal level, and the gate electrodes of the first switching transistor and the current control transistor are each disposed at a row select line of the matrix, on a gate metal level;

each pixel is disposed between two row select lines of the matrix, with the first current driver disposed between a first of these two row select lines and the pixel electrode, said first row select line forming the gate of the first switching transistor of the first current driver and the second current driver is disposed between a second of these two row select lines and the pixel electrode, said second row select line forming the gate of the first switching transistor of the second current driver;

a source-drain electrode of the current control transistors of the first and second current drivers is formed by a Vdd supply bus produced on the source-drain metal level, and the other source-drain electrode of the control transistors is formed by an excrescence of the pixel electrode on the source-drain metal level; and

each column data line is disposed between two columns of pixels of the matrix and formed from said source-drain metal level and said gate metal level, said gate metal level being used along the pixel electrodes and said source-drain metal level being used in zones between said pixel electrodes where the first switching transistors of said first and second current drivers are disposed.

2. The matrix according to claim 1 , wherein said supply voltage Vdd is distributed over the matrix by the Vdd supply bus with a row/column matrixed arrangement.

3. The matrix according to claim 2 , wherein each area between two successive columns of pixels comprises the Vdd supply bus and at least one column data line conductor.

4. The matrix according to claim 2 , wherein the first switching transistor of the first current driver for a first pixel and the first switching transistor of the second current driver for another pixel are placed back-to-back and on either side of a row select line.

5. The matrix according to claim 4 , wherein each area between two successive columns of pixels comprises the Vdd supply bus column and a column data line conductor, and said first switching transistors placed back-to-back have a source-drain electrode formed by a portion of a source-drain metal column conductor of the column data line conductor.

6. The matrix according to claim 2 , wherein the control transistor of the first current driver of a first pixel and the control transistor of the second current driver of a preceding or following pixel are arranged symmetrically on either side of a row select line.

7. The matrix according to claim 2 , wherein the control transistors of said first and second current drivers have interdigitated source-drain electrodes, each source-drain electrode comprising more than one finger.

8. The matrix according to claim 1 , wherein

each first current driver and each second current driver comprises a second switching transistor connected between the row select line, to which the gate of the first switching transistor of the first current driver and second current driver is connected, respectively, and the gate of said control transistor, and

the gate of the second switching transistor is connected to another row select line, wherein each row select line is divided in an active zone into a first branch and a second branch placed on either side of a corresponding row of pixels.

9. The matrix according to claim 8 , wherein the supply voltage Vdd is distributed by column conductors, with a supply column conductor in each area between two columns of pixels, and in which the control transistors of the first and second current drivers of a pixel are produced along the pixel electrode, between said pixel electrode and said supply column conductor which form, respectively, a first source-drain electrode and a second source-drain electrode of said control transistors.

10. A display screen comprising:

organic light-emitting diodes, each including an active matrix according to any one of the preceding claims.

Assignments (4)
CORRECTIVE ASSIGNMENT TO CORRECT THE RECEIVING PARTY NAME FROM INTERDIGITAL CE PATENT HOLDINGS TO INTERDIGITAL CE PATENT HOLDINGS, SAS. PREVIOUSLY RECORDED AT REEL: 47332 FRAME: 511. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Feb 28, 2024
From: THOMSON LICENSING
To: INTERDIGITAL CE PATENT HOLDINGS, SAS
Reel/Frame 066703/0509 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 26, 2018
From: THOMSON LICENSING
To: INTERDIGITAL CE PATENT HOLDINGS
Reel/Frame 047332/0511 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 1, 2017
From: THALES
To: THOMSON LICENSING
Reel/Frame 043468/0933 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 2, 2008
From: KRETZ, THIERRY; LEBRUN, HUGUES; CHUITON, ELISABETH
To: THALES
Reel/Frame 021025/0445 →
Priority Claims (1)
FR 07 01929 · Mar 16, 2007 · national
Continuity (1)
Related Publication 20080231556A1 · Sep 25, 2008