Memory with write port configured for double pump write
View Patent ↗A memory with a write port configured for double-pump writes. The memory includes a first and second memory locations each having one or more bit cells, and one or more bit lines each coupled to corresponding ones of the bit cells. A write port is coupled to each of the bit lines. Selection circuitry, responsive to a first clock edge, latches first data from a first data path through the write port, and responsive to a second clock edge, latches second data from a second data path through the write port. A first pulse is generated during a first phase of the clock signal to cause writing of the first data into the first memory location. A second pulse is generated during a second phase of the clock signal to cause writing of the second data into the second memory location.
1. A method of writing to a memory, the method comprising:
responsive to a first edge of clock signal, latching first data received from a first data path onto one or more bit lines each coupled between a write data port and a corresponding one of one or more bit cells of a first memory location, wherein each of the one or more bit lines are further coupled between the write data port and a corresponding one of one or more bit cells of a second memory location;
subsequent to the first edge, and during a first phase of a cycle of the clock signal, providing a first pulse on a first word line coupled to each of the bit cells of the first memory location, thereby capturing the first data into the first memory location;
responsive to a second edge of the clock signal, latching second data received from a second data path onto the one or more bit lines; and
subsequent to the second edge and during a second phase of the cycle of the clock signal, providing a second pulse on a second word line coupled to each of the bit cells of the second memory location, thereby capturing the second data into the second memory location.
2. The method as recited in claim 1 , wherein the duration of the first pulse is less than the duration of the first phase of the clock signal, and wherein the duration of the second pulse is less than the duration of the second phase of the clock signal.
3. The method as recited in claim 2 , wherein the duration of the first pulse and the length of the second pulse each have a duration of approximately one quarter of a cycle of the clock signal.
4. The method as recited in claim 2 , wherein the first pulse and the second pulse are generated using the clock signal.
5. The method as recited in claim 1 , wherein each of the one or more bit cells of the first memory location and the one or more bit cells of the second memory location are single-ended bit cells.
6. The method as recited in claim 1 , wherein the clock signal is high during one of the first phase or the second phase, and wherein the clock signal is low during the other one of the first phase or the second phase.
7. The method as recited in claim 6 , wherein one of the first edge or the second edge is a rising edge, and wherein the other one of the first edge or the second edge is a falling edge.