Memory interface and adaptive data access method
View Patent ↗A data access method for an application circuit to access a memory. The method includes steps of: receiving a first data from the application circuit; duplicating the first data to obtain a duplicated first data; and writing the first data and the duplicated first data into the memory at continuously accessible addresses. For accessing to the first data, the first data and the duplicated first data are read from the memory in response to a rising edge and a falling edge of a data-triggering signal; and one of the first data and the duplicated first data is outputted while the other of the first data and the duplicated first data is discarded.
1. A data access method for an application circuit to access a memory, comprising steps of:
receiving a first data from the application circuit;
determining whether the first data is audio/video data;
duplicating the first data to obtain a duplicated first data and writing the first data and the duplicated first data into the memory at continuously accessible addresses each time when the first data is not audio/video data; and
writing only the first data into the memory when the first data is audio/video data.
2. The data access method according to claim 1 further comprising steps of:
reading the first data from the memory in response to one of a rising edge and a falling edge of a data-triggering signal and the duplicated first data from the memory in response to the other of the rising edge and the falling edge of the data-triggering signal;
determining whether an outputted data is read in response to the rising edge or the falling edge; and
reading a subsequent first data or a duplicated first data corresponding to the subsequent first data from the memory in response to only the rising edge or falling edge resulting in the outputted data.
3. The data access method according to claim 2 further comprising steps of:
discarding one of the first data and the duplicated first data while outputting the other of the first data and the duplicated first data to the application circuit.
4. The data access method according to claim 1 further comprising steps of:
writing a second data which is received from the application circuit and classified as a second data type different from a first data type of the first data into the memory; and
reading the second data from the memory and outputting the second data to the application circuit in response to both rising and falling edges of a data-triggering signal.
5. The data access method according to claim 4 wherein the second data is an audio/video data.
6. The data access method according to claim 1 wherein the first data is program codes or a data required for executing a system program.
7. A data access method for an application circuit to access a memory, comprising steps of:
writing a first type of data and a second type of data into the memory, wherein the first type of data is program codes or data required for executing a system program and the second type of data is audio/video data;
lengthening an accessible period of the first type of data rather than the second type of data each time by duplicating the first type of data and writing the duplicated first data into the memory at continuously accessible addresses; and
reading the first type of data and the second type of data each in response to both rising and falling edges of a data-triggering signal.
8. The data access method according to claim 7 wherein the second type of data is read from the memory and outputted to the application circuit in response to both the rising and falling edges of the data-triggering signal.
9. The data access method according to claim 7 wherein the first type of data is read from the memory in response to both the rising and falling edges of the data-triggering signal and outputted to the application circuit in response to only one of the rising and falling edges of the data-triggering signal.
10. The data access method according to claim 7 wherein the accessible period of the first type of data is lengthen by:
duplicating the first type of data and writing the duplicated data into the memory at an address accessible next to the original data; and
triggering the reading of both the original data and the duplicated data within a single cycle of the data-triggering signal.
11. The data access method according to claim 10 further comprising a step of:
discarding one of the original data and the duplicated data and outputting the other of the original data and the duplicated data to the application circuit.
12. A memory interface for an application circuit to access a memory, comprising:
a first interface unit in communication with the application circuit for transmitting a first type of data between the application circuit and the memory;
a second interface unit in communication with the application circuit for transmitting a second type of data between the application circuit and the memory; and
a control unit in communication with the first interface unit, the second interface unit and the memory for conducting a first data access operation for the first type of data and conducting
a second data access operation for the second type of data;
wherein the first data access operation, including sequentially reading an original form of the first type of data and a duplication of the first type of data from the memory in a single cycle of a data-triggering signal, is conducted by the control unit when the first type of data is a program code or a data required for executing a system program each time;
wherein the second data access operation is conducted by the control unit when the second type of data is audio/video data.
13. The memory interface according to claim 12 wherein the first data access operation and the second data access operation are performed in response to the same data-triggering signal but result in different data access rates.
14. The memory interface according to claim 12 wherein the control unit includes:
a controller in communication with the first interface unit and the second interface unit for controlling one of the first data access operation and the second data access operation to be performed;
a data-duplicating unit in communication with the controller for duplicating the first type of data when the first data access operation is performed;
a data-writing unit coupled between the data-duplicating unit and the memory for writing the original and duplicated first type of data into the memory at continuously accessible addresses; and
a selecting unit coupled between the memory and the controller for reading the original and duplicated first type of data and selecting one of the original and duplicated first type of data to be outputted to the application circuit.
15. The memory interface according to claim 14 wherein the second type of data bypasses the data-duplicating unit and is directly written into the memory by the data-writing unit.
16. The memory interface according to claim 14 wherein the second type of data bypasses the selecting unit and is read to be outputted to the application circuit in response to both rising and falling edges of a data-triggering signal.
17. A memory interface for an application circuit to access a memory, comprising:
a detecting unit in communication with the application circuit for determining a data type of a data to be accessed by the application circuit; and
a control unit in communication with the detecting unit and the memory for conducting a first data access operation when the data to be accessed is a first type of data and conducting a second data access operation when the data to be accessed is a second type of data;
wherein the first data access operation, including sequentially reading an original first type of data and a duplicated first type of data having the same contents with each other, is conducted by the control unit when the first type of data is a program code or a data required for executing a system program each time;
wherein the second data access operation is conducted by the control unit when the second type of data is audio/video data.
18. The memory interface according to claim 17 wherein the first data access operation and the second data access operation are performed in response to the same data-triggering signal but result in different data access rates.
19. The memory interface according to claim 17 wherein the control unit includes:
a controller in communication with the detecting unit for controlling one of the first data access operation and the second data access operation to be performed according to the detected data type;
a data-duplicating unit in communication with the controller for duplicating the first type of data when the first data access operation is performed;
a data-writing unit coupled between the data-duplicating unit and the memory for writing the original and duplicated first type of data into the memory at continuously accessible addresses; and
a selecting unit coupled between the memory and the controller for reading the original and duplicated first type of data and selecting one of the original and duplicated first type of data to be outputted to the application circuit.
20. The memory interface according to claim 17 wherein the second type of data bypasses the data-duplicating unit and is directly written into the memory by the data-writing unit in a data-writing process, and the second type of data bypasses the selecting unit and is read to be outputted to the application circuit in a data-reading process.