Method of forming a gate layer with multiple ecthing steps
View Patent ↗A method of manufacturing a semiconductor device has forming a first silicon film over the first insulating film, forming a second silicon film over the first silicon film, a first etching the second silicon film in a depth, which the first silicon film is not exposed, in first condition, a second etching a remaining portion of the second silicon film and the first silicon film in a depth, which the first insulating film is not exposed, in second condition which gives a higher vertical etching component ratio than the first condition; and a third etching a remaining portion of the first silicon film in third condition which an etching rate for the first silicon film is larger than an etching rate for the first insulating film as compared to the second condition, wherein an impurity concentration of a first conductivity type of the first silicon film is higher than an impurity concentration of first conductivity type of the second silicon film.
1. A method of manufacturing a semiconductor device comprising:
forming a first insulating film over a semiconductor substrate;
forming a first silicon film over the first insulating film;
forming a second silicon film over the first silicon film;
forming a mask layer in a predetermined pattern over the second silicon film;
first etching the second silicon film in a depth such that the first silicon film is not exposed, in a first condition while using the mask layer as an etching mask;
second etching a remaining portion of the second silicon film and the first silicon film in a depth such that the first insulating film is not exposed, in a second condition which gives a higher vertical etching component ratio than the first condition; and
third etching a remaining portion of the first silicon film in a third condition of which a ratio of an etching rate for the first silicon film to an etching rate for the first insulating film is larger than that of the second condition,
wherein an impurity concentration of a first conductivity type in the first silicon film is higher than an impurity concentration of the first conductivity type in the second silicon film.
2. The method of claim 1 , wherein the second silicon film is etched in a depth which is 70% or more of a film thickness by the first etching.
3. The method of claim 1 , further comprising:
removing an oxide film over a surface of the second silicon film before the first etching.
4. The method of claim 1 , wherein a first reaction gas used for the first etching includes HBr and O 2 .
5. The method of claim 4 , wherein the first reaction gas further includes Cl 2 .
6. The method of claim 1 , wherein a thickness of the first silicon film removed by the second etching is 20 nm or more.
7. The method of claim 1 , wherein an impurity concentration of the first conductivity type in the first silicon film etched in the second etching is 1×10 18 atoms/cm 3 or more.
8. The method of claim 1 , wherein a second reaction gas used for the second includes CH x F y gas.
9. The method of claim 8 , wherein the CH x F y gas contains at least one of CH 2 F 2 , CHF 3 , and CH 3 F.
10. The method of claim 8 , wherein the second reaction gas contains at least one of Cl 2 , HBr, HI, and Br 2 .
11. The method of claim 8 , wherein a flow rate ratio of the CH x F y gas to a total flow rate of the second reaction gas is 2 to 5 flow rate %.
12. The method of claim 1 , wherein the third etching has a first step of executing an etching in the third condition, and a second step of executing an etching in fourth condition in which a ratio of an etching rate of the first silicon film to an etching rate of the first insulating film is set larger than the third condition.
13. The method of claim 1 , wherein the first insulating film includes a silicon oxide.
14. The method of claim 1 , wherein the first silicon film and the second silicon film are formed of either of a polysilicon film and an amorphous silicon film respectively.
15. The method of claim 1 , further comprising:
after the third etching, removing the mask layer;
forming a metal film over the second silicon film; and
forming a metal silicide film over the second silicon film by heating the metal film and the second silicon film.
16. The method of claim 1 , wherein the first silicon film and the second silicon film are patterned by the first etching, the second etching, and the third etching correspond to a gate electrode.
17. The method of claim 16 , further comprising:
after the third etching, forming a second insulating film over an overall surface of the semiconductor substrate;
etching back the second insulating film to leave over side surfaces of the gate electrode as a sidewall spacer; and
forming the source/drain region by introducing an impurity into the semiconductor substrate while using the gate electrode and the sidewall spacer as a mask.
18. The method of claim 17 , further comprising:
in a case that at least one of the first silicon film and the second silicon film is formed of amorphous film, after forming the second insulating film but before etching back the second insulating film, crystallizing the amorphous film by heating the first silicon film or the second silicon film.