DRIVING METHOD OR APPARATUS FOR FLAT PANEL DISPLAY DEVICE
A driving circuit board for a flat panel display device includes a substrate having a first surface and a second, opposite surface. A first timing controller is disposed on the first surface, and a second timing controller is disposed on the second surface of the substrate. At least one electrically conductive line electrically connects input terminals of the first and second timing controllers through the substrate.
1 . A driving circuit board for a flat panel display device, the driving circuit board comprising:
a substrate having a first surface and a second surface opposite to the first surface;
a first timing controller disposed on the first surface of the substrate and having at least one first input terminal;
a second timing controller disposed on the second surface of the substrate and having at least one second input terminal; and
at least one first electrically conductive line electrically connecting the first input terminal and the second input terminal through the substrate.
2 . The driving circuit board according to claim 1 , wherein the electrically conductive line further comprises at least one first conductive via for connecting the first surface with the second surface, and the first metal line further has a first segment electrically connecting the first input terminal to the first conductive via and a second segment electrically connecting the second input terminal to the first conductive via.
3 . The driving circuit board according to claim 1 , wherein the first timing controller has at least one first output terminal, and the second timing controller has at least one second output terminal.
4 . The driving circuit board according to claim 3 , further comprising at least one second electrically conductive line electrically connecting the first output terminal to a display panel.
5 . The driving circuit board according to claim 3 , further comprising at least one third electrically conductive line electrically connecting the second output terminal to a display panel.
6 . The driving circuit board according to claim 1 , wherein the first input terminal of the first timing controller is adjacent to a projected position of the second input terminal of the second timing controller.
7 . The driving circuit board according to claim 1 , wherein the first timing controller has plural first input terminals, and the second timing controller has plural second input terminals, and the driving circuit board has additional electrically conductive lines, the first and additional electrically conductive lines to electrically connect respective first input terminals to corresponding second input terminals.
8 . The driving circuit board of claim 7 , wherein the first and additional electrically conductive lines are generally parallel to each other.
9 . The driving circuit board according to claim 1 , further comprising an image processor having at least one image output terminal electrically connected to the first input terminal of the first timing controller and the second input terminal of the second timing controller.
10 . The driving circuit board according to claim 1 , wherein the flat panel display device is a liquid crystal display (LCD) device.
11 . A driving system for a flat panel display device, the driving system comprising:
a first timing controller if enabled for receiving a plurality of pixel data signals and outputting a first portion of the pixel data signals; and
a second timing controller if enabled for receiving the pixel data signals and outputting a second portion of the pixel data signals.
12 . The driving system according to claim 11 , further comprising a selection mechanism to selectively enable one or both of the first and second timing controllers.
13 . The driving system according to claim 12 , wherein the selection mechanism comprises a firmware setting in each of the first and second timing controllers.
14 . The driving system of claim 11 , wherein if just one of the first and second timing controllers is enabled, the enabled one of the first timing controllers receives the pixel data signals and outputs an entirety of the receiver pixel data signals.
15 . The driving system according to claim 11 , further comprising an image processor for outputting the pixel data signals.
16 . The driving system according to claim 11 , further comprising at least one first driving circuit and at least one second driving circuit electrically connected with a pixel array region of a display panel, wherein the first driving circuit receives the first portion of the pixel data signals outputted from the first timing controller, and the second driving circuit receives the second portion of the pixel data signals outputted from the second timing controller to respectively drive a first sub-region of the pixel array region and a second sub-region of the pixel array region to display the pixel data signals.
17 . The driving system according to claim 16 , wherein the first driving circuit and the second driving circuit are data line driving circuits.
18 . The driving system according to claim 16 , wherein the first driving circuit and the second driving circuit are disposed in the display panel.
19 . The driving system according to claim 11 , further comprising:
a selector for generating at least one selection signal to selectively enable one of the first and second timing controllers, wherein the first timing controller and the second timing controller output the pixel data signals according to the at least one selection signal.
20 . The driving system according to claim 11 , further comprising a third timing controller for receiving the pixel data signals and outputting a third portion of the pixel data signals.
21 . A driving method for a flat panel display device being used in conjunction with a driving system, the driving system comprising a first timing controller and a second timing controller, the driving method comprising:
receiving a plurality of pixel data signals and outputting a first portion of the pixel data signals by the first timing controller if the first timing controller is enabled; and
receiving the pixel data signals and outputting a second portion of the pixel data signals by the second timing controller if the second timing controller is enabled.
22 . The driving method according to claim 21 , further comprising detecting a setting to determine whether just one of the first and second timing controllers is to be enabled or whether both the first and second timing controllers are to be enabled.
23 . The driving method according to claim 22 , wherein if one of the first and second timing controllers is disabled, the other of the first and second timing controllers receives the pixel data signals to output an entirety of the pixel data signals.
24 . The method according to claim 21 , wherein the driving system further comprises an image processor for, and the method further comprises:
outputting the pixel data signals to the first timing controller and the second timing controller by the image processor.
25 . The method according to claim 21 , wherein the driving system further comprises at least one first driving circuit and at least one second driving circuit, and the method further comprises:
receiving the first portion of the pixel data signals outputted from the first timing controller by the first driving circuit and receiving the second portion of the pixel data signals outputted from the second timing controller by the second driving circuit so as to respectively drive a first sub-region of the pixel array region and a second sub-region of the pixel array region to display the pixel data signals.
26 . The method according to claim 21 , wherein the driving system further comprises a selector, and the method further comprises:
generating at least one selection signal by the selector, wherein the first timing controller and the second timing controller output the pixel data signals according to the at least one selection signal.
27 . The method according to claim 26 , wherein the first timing controller and the second timing controller decide to output the first portion or the second portion of the pixel data signals according to the at least one selection signal.