Semiconductor integrated circuit and memory checking method
View Patent ↗The semiconductor integrated circuit includes a memory for storing secret data, a memory BIST circuit for executing a memory. BIST, a first selector for switching between a path for a memory isolation test via an external terminal and a path from the memory BIST circuit, a second selector for switching between a path from the output of the first selector and a path from a normal circuit and having an output coupled to the memory, and a third selector for switching between a path from the output of the memory and a path for receiving a pseudo signal and receiving a check completion signal outputted from the memory BIST circuit as a selection signal. In this semiconductor integrated circuit, after the memory is initialized by executing the memory BIST, the memory can be accessed from the external terminal via the path for the memory isolation test.
1. A semiconductor integrated circuit, comprising:
a memory which stores secret data;
a memory BIST circuit which executes a memory BIST with respect to the memory;
a first selector which switches between a path for a memory isolation test executed with respect to the memory via an external terminal and a path from the memory BIST circuit;
a second selector which switches between a path from an output of the first selector and a path from a normal circuit and has an output coupled to the memory; and
a third selector which switches between a path from an output of the memory and a path for receiving a pseudo signal and receives a check completion signal outputted from the memory BIST circuit as a selection signal,
wherein after the memory is initialized by executing the memory BIST, the memory can be accessed from the external terminal via the path for the memory isolation test.
2. The semiconductor integrated circuit according to claim 1 , further comprising:
another memory which stores dummy data different from the secret data, wherein the third selector switches between the path from the output of the memory and a path from an output of the another memory.
3. The semiconductor integrated circuit according to claim 1 , wherein the memory has a redundant area, and the third selector switches between the path from the output of the memory and a path from an output of the redundant area within the memory.
4. The semiconductor integrated circuit according to claim 1 , wherein a flip-flop of the normal circuit, a flip-flop of the memory BIST circuit and a flip-flop for observation are disposed on a same scanning chain, and the secret data stored in the memory is rewritten simultaneously with a shift operation at a time of a scanning test.
5. A method of checking a memory performed by a semiconductor integrated circuit, which includes:
the memory which stores secret data;
a memory BIST circuit which executes a memory BIST with respect to the memory;
a first selector which switches between a path for a memory isolation test executed with respect to the memory via an external terminal and a path from the memory BIST circuit;
a second selector which switches between a path from the output of the first selector and a path from a normal circuit and has an output coupled to the memory; and
a third selector which switches between a path from the output of the memory and a path for receiving a pseudo signal and receives a check completion signal outputted from the memory BIST circuit as a selection signal, the method comprising the step of:
at a time of checking the memory, the checking is performed from the external terminal via the path for the memory isolation test after the memory BIST circuit executes the memory BIST.