IP Library Granted Patent US 8,286,137
Granted Patent B2
US 8,286,137 · App. 12/054,575 · Granted Oct 9, 2012

Accelerating model checking via synchrony

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Quick Facts
Patent No.
US 8,286,137
App. No.
12/054,575
Granted
Oct 9, 2012
Kind
B2
Abstract

A system and method for program verification by model checking in concurrent programs includes modeling each of a plurality of program threads as a circuit model, and generating a full circuit for an entire program by combining the circuit models including constraints which enforce synchronous execution of the program threads. The program is verified using the synchronous execution to reduce an amount of memory needed to verify the program and a number of steps taken to uncover an error.

Claims (9)

1. A computer implemented method for program verification by via bounded or unbounded model checking in concurrent programs, comprising:

modeling each of a plurality of program threads as a circuit model;

generating a full circuit for an entire program by combining the circuit models including constraints which enforce synchronous execution of the program threads; and

verifying the program using the synchronous execution to reduce the amount of memory needed to verify the program and a number of steps taken to uncover an error; wherein using the synchronous execution includes determining synchronous conflicts conflicts to determine the subset of transitions that must be explored from each global state.

2. The method as recited in claim 1 , further comprising leveraging synchronous execution to reduce,the depth of computations explored during model checking.

3. The method as recited in claim 1 , wherein verifying includes:

checking necessary interleavings induced by shared variable updates and synchronization primitives by switching from interleaving to synchronous semantics while preserving a temporal property being model checked; and

integrating synchronous execution with partial order reduction, transactions and symbolic model checking.

4. The method as recited in claim 1 , wherein using the synchronous execution includes determining synchronous conflicts.

Assignments (3)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE 8223797 ADD 8233797 PREVIOUSLY RECORDED ON REEL 030156 FRAME 0037. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded May 30, 2017
From: NEC LABORATORIES AMERICA, INC.
To: NEC CORPORATION
Reel/Frame 042587/0845 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 5, 2013
From: NEC LABORATORIES AMERICA, INC.
To: NEC CORPORATION
Reel/Frame 030156/0037 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 13, 2008
From: KAHLON, VINEET; GUPTA, AARTI
To: NEC LABORATORIES AMERICA, INC.
Reel/Frame 020939/0673 →