IP Library Granted Patent US 8,072,199
Granted Patent B2
US 8,072,199 · App. 12/054,785 · Granted Dec 6, 2011

Control circuit for step-down DC-DC converter, step-down DC-DC converter and control method thereof

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Quick Facts
Patent No.
US 8,072,199
App. No.
12/054,785
Granted
Dec 6, 2011
Kind
B2
Abstract

To provide a control circuit of a step-down DC-DC converter, a step-down DC-DC converter and a control method thereof which can prevent overshoot and production of a through current flowing to a main switching transistor and a synchronous rectifier transistor by adopting a simple circuit configuration. The control circuit of the step-down DC-DC converter in which a main switching transistor M 0 is constituted of a NMOS transistor has a MOS transistor M 2 connected between a gate of the main switching transistor M 0 and a ground potential and is operable to become conductive in response to an OFF command from the main switching transistor M 0.

Claims (41)

1. A control circuit of a step-down DC-DC converter comprising a main switching transistor corresponding to an NMOS transistor,

wherein the step-down DC-DC converter comprises:

a MOS transistor, coupled between a gate of the main switching transistor and a ground potential, conducts in accordance with an OFF command of the main switching transistor;

a driver driving the gate of the main switching transistor by drive voltage of which high level input to be inputted into the gate of the main switching transistor is higher than input voltage to be inputted into a drain of the main switching transistor;

a detection unit detecting that the drive voltage is lower than a predetermined level; and

a control unit bringing the MOS transistor into conduction by the OFF command of the main switching transistor in accordance with a detection result of the detection unit,

wherein the main switching transistor is turned on by the drive voltage.

2. The control circuit of the step-down DC-DC converter according to claim 1 , wherein a ground-side terminal of the driver is coupled to a source of the main switching transistor.

3. The control circuit of the step-down DC-DC converter according to claim 1 , further comprising:

a synchronous rectification transistor.

4. The control circuit of the step-down DC-DC converter according to claim 3 , further comprising:

a first delay unit delaying a conduction control of the main switching transistor in accordance with an OFF command of the synchronous rectification transistor; and

a second delay unit delaying a conduction control of the synchronous rectification transistor in accordance with the OFF command of the main switching transistor.

5. A step-down DC-DC converter comprising a main switching transistor corresponding to an NMOS transistor,

wherein the step-down DC-DC converter further comprises:

a MOS transistor, coupled between a gate of the main switching transistor and a ground potential, conducts in accordance with an OFF command of the main switching transistor;

a driver driving the gate of the main switching transistor by drive voltage of which high level input to be inputted into the gate of the main switching transistor is higher than input voltage to be inputted into a drain of the main switching transistor;

a detection unit detecting that the drive voltage is lower than a predetermined level; and

a control unit bringing the MOS transistor into conduction by the OFF command of the main switching transistor in accordance with a detection result of the detection unit,

wherein the main switching transistor is turned on by the drive voltage.

6. The step-down DC-DC converter according to claim 5 , further comprising:

a drive voltage generating unit generating the drive voltage.

7. The step-down DC-DC converter according to claim 5 , wherein a ground-side terminal of the driver is connected to a source of the main switching transistor.

8. The step-down DC-DC converter according to claim 5 , further comprising:

a synchronous rectification transistor.

9. The step-down DC-DC converter according to claim 8 , further comprising:

a first delay unit delaying a conduction control of the main switching transistor in accordance with an OFF command of the synchronous rectification transistor; and

a second delay unit delaying a conduction control of the synchronous rectification transistor in accordance with the OFF command of the a main switching transistor.

10. A control method of a step-down DC-DC converter comprising a main switching transistor corresponding to an NMOS transistor, the control method comprising:

issuing an OFF command of the main switching transistor;

generating a path between a gate of the main switching transistor and a ground potential by conduction of a MOS transistor in accordance with the OFF command of the main switching transistor;

driving the gate of the main switching transistor in which a high level input of drive voltage to be inputted into the gate of the main switching transistor is made higher than input voltage to be inputted into a drain of the main switching transistor;

detecting that the drive voltage is lower than a predetermined level; and

bringing the MOS transistor into conduction by the OFF command of the main switching transistor in accordance with a result of the detecting,

wherein the main switching transistor is turned on by the drive voltage.

11. A step-down DC-DC converter comprising:

a first transistor comprising a first drain coupled to a first potential line and a first source coupled to an inductor;

a first driver driving a first gate of the first transistor by a first drive voltage, a potential of the first drive voltage being higher than the potential of the first potential line;

a second transistor, which forms a bath between the first gate of the first transistor and a second potential line by conduction, comprising a second drain coupled to the first gate of the first transistor and a second source coupled to a second potential line, a potential of the second potential line being lower than a potential of the first potential line; and

a second driver driving a second gate of the second transistor by a second drive voltage which changes in opposite phase with the first drive voltage,

wherein a conductivity type of the second transistor is same as a conductivity type of the first transistor.

Assignments (6)
CORRECTIVE ASSIGNMENT TO CORRECT THE 8647899 PREVIOUSLY RECORDED ON REEL 035240 FRAME 0429. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTERST. Recorded Nov 3, 2020
From: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 058002/0470 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN INTELLECTUAL PROPERTY Recorded Oct 28, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: MUFG UNION BANK, N.A.
Reel/Frame 050896/0366 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 25, 2019
From: CYPRESS SEMICONDUCTOR CORPORATION
To: MONTEREY RESEARCH, LLC
Reel/Frame 050829/0230 →
PARTIAL RELEASE OF SECURITY INTEREST IN PATENTS Recorded Sep 26, 2019
From: MUFG UNION BANK, N.A., AS COLLATERAL AGENT
To: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
Reel/Frame 050500/0112 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 11, 2013
From: FUJITSU SEMICONDUCTOR LIMITED
To: SPANSION LLC
Reel/Frame 031205/0461 →
CHANGE OF NAME Recorded Jul 22, 2010
From: FUJITSU MICROELECTRONICS LIMITED
To: FUJITSU SEMICONDUCTOR LIMITED
Reel/Frame 024748/0328 →