Methods and systems for calibrating a pipelined analog-to-digital converter
View Patent ↗A pipelined analog-to-digital converter includes a plurality of stages, each stage comprising an analog-to-digital converter (ADC) and a digital-to-analog converter (DAC). A method for increasing the accuracy of the pipelined ADC includes calibrating the ADC in each stage of the analog-to-digital converter by adjusting trip points of that ADC. Another method for increasing the accuracy of a pipelined ADC includes measuring error in an output of each the DAC; and correcting an output of the pipelined analog-to-digital converter for the measured error. These methods can be used together to further increase the accuracy of the pipelined ADC. Consequently, a pipelined analog-to-digital converter may include a look-up table containing data for correcting errors in output of each of the DACs, where trip points of the ADCs the ADCs in the stages of the pipelined converter have been calibrated to expected values.
1. A method for increasing accuracy of a pipelined analog-to-digital converter comprising a plurality of stages, each stage comprising an analog-to-digital converter (ADC) and a digital-to-analog converter (DAC), said method comprising:
calibrating said ADC in each stage of said analog-to-digital converter by adjusting trip points of that ADC; and
driving each said ADC in each stage of said pipelined analog-to-digital converter with a reference DAC to determine what adjustment to make to said trip points of that ADC,
in which said trip points are adjusted by modifying a reference input to a comparator of said ADC.
2. The method of claim 1 , further comprising driving each said ADC in each stage of said pipelined analog-to-digital converter with a reference DAC to determine what adjustment to make to said trip points of that ADC.
3. The method of claim 2 , further comprising calibrating first the ADC in a last stage of said pipelined ADC.
4. The method of claim 1 , wherein said pipelined ADC is a current mode pipelined ADC.
5. The method of claim 1 , further comprising:
measuring error in an output of each said DAC; and
correcting an output of said pipelined analog-to-digital converter for said measured error.
6. The method of claim 5 , further comprising:
storing information about measured errors in the output of said DACs in a look-up table; and
generating a signal for correcting said output of said pipelined analog-to-digital converter using said look-up table.
7. The method of claim 6 , wherein said signal for correcting said output of said pipelined analog-to-digital converter is a digital signal.
8. The method of claim 5 , wherein said pipelined analog-to-digital converter is a current mode pipelined analog-to-digital converter.
9. A method for increasing accuracy of a pipelined analog-to-digital converter comprising a plurality of stages, each stage comprising an analog-to-digital converter (ADC) and a digital-to-analog converter (DAC), said method comprising:
calibrating each said ADC starting from a least significant stage until all ADCs have been calibrated using a reference digital-to-analog converter, said reference digital-to-analog converter selectively outputting values at desired trip points for each said ADC;
measuring error in an output of each said DAC; and
correcting an output of said pipelined analog-to-digital converter for said measured error, in which said trip points are adjusted by modifying a reference current input to a comparator of each said ADC.
10. The method of claim 9 , further comprising:
storing information about measured errors in the output of said DACs in a look-up table; and
generating a signal for correcting said output of said pipelined analog-to-digital converter using said look-up table.
11. The method of claim 10 , wherein said signal for correcting said output of said pipelined analog-to-digital converter is a digital signal.
12. The method of claim 9 , wherein said pipelined analog-to-digital converter is a current mode pipelined analog-to-digital converter.
13. A pipelined analog-to-digital converter comprising:
a plurality of stages, each stage comprising an analog-to-digital converter (ADC) and a digital-to-analog converter (DAC); and
a look-up table containing data for correcting errors in output of each of said DACs;
wherein trip points of said ADCs in said stages of said pipelined converter have been calibrated to expected values,
in which each of said ADCs in said stages of said pipelined converter comprise comparators with reference inputs adjusted to calibrate said trip points.
14. The converter of claim 13 , in which said reference inputs adjusted to calibrate said trip points are current sources.
15. The converter of claim 13 , wherein each of said ADCs in said stages of said pipelined converter comprise current mini-DACs adjusted to calibrate said trip points.
16. The converter of claim 13 , wherein said pipelined analog-to-digital converter is a current mode pipelined analog-to-digital converter.
17. The converter of claim 13 , further comprising a reference DAC for outputting reference signals to said ADCs in said stages of said pipelined converter to generate the data stored in said look-up table.
18. The converter of claim 17 , wherein a step output of said reference DAC is summed with a step output of said DAC of a particular stage of said pipelined converter to generate look-up table data for that stage of said pipelined converter.
19. The method of claim 1 , in which a nonlinearity of a stage is at least partially corrected by adjusting a gain between said stage and a next stage using an output of said ADC after calibration.
20. The method of claim 6 , in which said information about measured errors comprises corrected step sizes.