High-speed receiver architecture
View Patent ↗A receiver (e.g., for a 10 G fiber communications link) includes an interleaved ADC coupled to a multi-channel equalizer that can provide different equalization for different ADC channels within the interleaved ADC. That is, the multi-channel equalizer can compensate for channel-dependent impairments. In one approach, the multi-channel equalizer is a feedforward equalizer (FFE) coupled to a Viterbi decoder, for example a sliding block Viterbi decoder (SBVD); and the FFE and/or the channel estimator for the Viterbi decoder are adapted using the LMS algorithm.
1. A timing recovery circuit for use in a high-speed receiver comprising:
a timing phase corrector to apply a phase correction to an input signal using a first filter, wherein a coefficient of the first filter is dynamically adjusted based on an error signal;
a pulse preprocessor coupled to the timing phase corrector to apply a second filter to an output of the timing phase corrector, the second filter shaping the output of the timing phase corrector to produce an output signal suitable for phase detection; and
a phase detector coupled to the pulse preprocessor to detect phase of the output signal from the pulse pre-processor; and
a circuit for determining a performance measure of the receiver based on the detected phase and generating the error signal based on the performance measure.
2. The timing recovery circuit of claim 1 wherein the high-speed receiver comprises an interleaved ADC that decimates a serial data stream into N parallel data streams and the timing phase corrector receives parallel inputs of the N data streams from the interleaved ADC, wherein N is an integer ≧2.
3. The timing recovery circuit of claim 2 wherein the timing phase corrector receives more than N parallel inputs of the N data streams from the interleaved ADC.
4. The timing recovery circuit of claim 2 wherein the timing phase corrector implements a two-tap causal filter.
5. The timing recovery circuit of claim 2 wherein the timing phase corrector implements F(z)=1−αz −1 , with |α|<<1.
6. The timing recovery circuit of claim 2 wherein the pulse preprocessor implements a causal filter with not more than three taps.
7. The timing recovery circuit of claim 2 wherein the pulse preprocessor implements G(z)=0.5+z −1 +0.5z −2 .
8. The timing recovery circuit of claim 2 wherein the phase detector is clocked at a rate of the N parallel data streams rather than a rate of the serial data stream.
9. The timing recovery circuit of claim 2 wherein the timing phase corrector, pulse preprocessor and phase detector collectively comprise a phase detector preprocessor.
10. The timing recovery circuit of claim 9 wherein the phase detector preprocessor receives N+k parallel inputs of the N data streams where k>0, and produces M outputs where M≧2.
11. The timing recovery circuit of claim 10 wherein the phase detector preprocessor comprises N lattice circuits and M adder trees, each lattice circuit receiving k of the N+k parallel inputs of the N data streams and producing M outputs, each adder tree receiving one of the M outputs from each of the N lattice circuits and producing one of the M outputs of the phase detector preprocessor.
12. The timing recovery circuit of claim 11 wherein the lattice circuits implement the timing phase corrector and pulse preprocessor.
13. The timing recovery circuit of claim 11 wherein the timing phase corrector implements a two-tap causal filter, and the pulse preprocessor implements a causal filter with not more than three taps.
14. The timing recovery circuit of claim 2 wherein N=8.
15. The timing recovery circuit of claim 2 wherein the serial data stream is a 10 G data stream, and the N parallel data streams are eight 1.25 G data streams.
16. The timing recovery circuit of claim 2 wherein N is a power of two.
17. A timing recovery circuit for use in a high-speed receiver, wherein the high-speed receiver comprises an interleaved ADC that decimates a serial data stream into N parallel data streams where N is an integer ≧2, the timing recovery circuit comprising:
means for timing phase correction, said means receiving parallel inputs of the N data streams from the interleaved ADC and applying a first filter to the N data streams, wherein a coefficient of the first filter is dynamically adjusted based on an error signal;
means for pulse preprocessing coupled to the means for timing phase correction, the means for pulse preprocessing applying a second filter to an output of the means for timing phase correction, the second filter shaping the output of the means for timing phase correction to produce an output signal suitable for phase detection; and
means for phase detection coupled to the means for pulse preprocessing, the means for phase detection detecting a phase of the output signal from the pulse pre-processor.
18. A method for timing recovery comprising:
receiving N parallel data streams, the N parallel data streams created by decimating a serial data stream, where N is an integer ≧2;
performing, by a timing recovery circuit, timing phase correction on each of the N parallel data streams to correct a phase of each of the N parallel data streams;
performing, by the timing recovery circuit, pulse preprocessing on each of the N timing phase corrected data streams to shape each of the N timing phase corrected data streams to produce shaped pulse signals suitable for phase detection; and
performing, by the timing recovery circuit, phase detection on the pulse preprocessed data streams to detect phase of the output signal from the pulse pre-processor.
19. The method of claim 18 wherein the step of timing phase correction comprises applying a two-tap causal filter, and the step of pulse preprocessing comprises applying a causal filter with not more than three taps.
20. The method of claim 18 wherein the step of performing phase detection is clocked at a rate of the N parallel data streams rather than a rate of the serial data stream.