A heterojunction bipolar transistor comprising a substrate; a collector on the substrate; a base layer on the collector; an emitter layer on the base layer; the emitter layer comprising an upper emitter layer and a lower emitter layer between the upper emitter layer and base; the collector, base and emitter layers being npn or pnp doped respectively; characterized in that the lower emitter layer has a larger bandgap than the base layer and is Al x In 1-x P or Ga x Al 1-x P, x being in the range 0 + to 1.
1. A heterojunction bipolar transistor comprising:
a substrate;
a collector on the substrate;
a base layer on the collector; an emitter layer on the base layer;
the emitter layer comprising an upper emitter layer and a lower emitter layer between the upper emitter layer and the base layer;
the collector, base and emitter layers being npn or pnp doped respectively;
characterised in that the lower emitter layer has a larger bandgap than the base layer and is Al x In 1-x P such that 0<x<1.
2. A heterojunction bipolar transistor as claimed in claim 1 wherein x is in the range 0.05 to 0.95.
3. A heterojunction bipolar transistor as claimed in claim 1 wherein the transistor is an npn transistor with the collector and emitter layers being n doped and the base layer being p doped.
4. A heterojunction bipolar transistor as claimed in claim 1 wherein the transistor is a pnp transistor with the collector and emitter layers being p doped and the base layer being n doped.
5. A heterojunction bipolar transistor as claimed in claim 1 wherein the upper emitter layer is GaAs.
6. A heterojunction bipolar transistor as claimed in claim 5 , wherein the emitter further comprises an AlGaAs grading layer between the GaAs upper emitter layer and the lower emitter layer.
7. A heterojunction bipolar transistor as claimed in claim 6 further comprising an InGaAs contact layer on the emitter layer.
8. A heterojunction bipolar transistor as claimed in claim 7 , further comprising an emitter electrode on the contact layer.
9. A heterojunction bipolar transistor as claimed in claim 7 further comprising an InGaAs graded composition layer between the InGaAs contact layer and the emitter layer.
10. A heterojunction bipolar transistor as claimed in claim 1 further comprising a base electrode on the base layer.
11. A heterojunction bipolar transistor as claimed in claim 1 wherein the lower emitter layer extends beyond the upper emitter layer in the plane of the base to form a covering layer on the base, the heterojunction bipolar transistor further comprising a base electrode on the covering layer.
12. A heterojunction bipolar transistor as claimed in claim 1 wherein the base layer is Ga 1-x In x As 1-y N y , with x and y each being in the range 0 to 1.
13. A heterojunction bipolar transistor as claimed in claim 12 , wherein the base is GaAs.
14. A heterojunction bipolar transistor as claimed in claim 1 wherein the collector is GaAs.
15. A heterojunction bipolar transistor as claimed in claim 14 , wherein the collector is divided into an upper collector portion and a subcollector portion.
16. A heterojunction bipolar transistor as claimed in claim 15 , when dependant on claim 6 , wherein the upper collector portion is n-GaAs and the subcollector is n + GaAs.
17. A heterojunction bipolar transistor as claimed in claim 15 comprising an etch stop layer between the upper collector and sub collector portions.
18. A heterojunction bipolar transistor as claimed in claim 17 wherein the etch stop layer comprises Al x In 1-x P, x being in the range 0 + to 1.
19. A heterojunction bipolar transistor as claimed in claim 17 , wherein the etch stop layer comprises Ga x In 1-x P, x being in the range 0 + to 1.
20. A heterojunction bipolar transistor as claimed in claim 17 , wherein the etch stop layer comprises Al x In 1-x P, x being in the range 0.05 to 0.95.
21. A heterojunction bipolar transistor as claimed in claim 17 , wherein the etch stop layer comprises Al x In 1-x P, x being in the range 0.4 to 0.6.
22. A heterojunction bipolar transistor as claimed in claim 17 , wherein the etch stop layer comprises Al x In 1-x P, x being 0.5.
23. A heterojunction bipolar transistor as claimed in claim 17 , wherein the etch stop layer comprises Ga x In 1-x P, x being in the range 0.05 to 0.95.
24. A heterojunction bipolar transistor as claimed in claim 17 , wherein the etch stop layer comprises Ga x In 1-x P, x being in the range 0.4 to 0.6.
25. A heterojunction bipolar transistor as claimed in claim 17 , wherein the etch stop layer comprises Ga x In 1-x P, x being 0.5.
26. A heterojunction bipolar transistor as claimed in claim 15 further comprising a collector electrode on the subcollector portion.
27. A heterojunction bipolar transistor as claimed in claim 1 wherein the substrate is a semi insulating GaAs substrate.
28. A heterojunction bipolar transistor as claimed in claim 1 , wherein x is in the range 0.4 to 0.6.
29. A heterojunction bipolar transistor as claimed in claim 1 , wherein x is 0.5.
30. A multilayer semiconductor wafer comprising;
a substrate;
a collector layer on the substrate;
a base layer on the collector layer;
an emitter layer on the base layer;
the emitter layer comprising an upper emitter layer and a lower emitter layer between the upper emitter layer and the base layer;
the collector, base and emitter layers being npn or pnp doped respectively;
characterized in that the lower emitter layer has a larger bandgap than the base layer and is Al x In 1-x P, such that 0<x<1.
31. A multilayer semiconductor wafer as claimed in claim 30 wherein x is in a range 0.05 to 0.95.
32. A multilayer semiconductor wafer as claimed in claim 30 wherein the upper emitter layer is GaAs.
33. A multilayer semiconductor wafer as claimed in claim 32 , further comprising an AlGaAs grading layer between upper emitter layer and lower emitter layer.
34. A multilayer semiconductor wafer as claimed in claim 30 further comprising an InGaAs contact layer on the upper emitter layer.
35. A multilayer semiconductor wafer as claimed in claim 34 further comprising an InGaAs graded composition layer between the contact layer and upper emitter layer.
36. A multilayer semiconductor wafer as claimed in claim 30 wherein the collector and emitter layers are n doped and the base layer is p doped.
37. A multilayer semiconductor wafer as claimed in claim 30 wherein the collector and emitter layers are p doped and the base layer is n doped.
38. A multilayer semiconductor wafer as claimed in claim 30 , wherein x is in the range 0.4 to 0.6.
39. A multilayer semiconductor wafer as claimed in claim 30 , wherein x is 0.5.
40. A PNP heterojunction bipolar transistor comprising:
a substrate;
a collector layer on the substrate;
a base layer on the collector layer;
an emitter layer on the base layer;
the emitter layer comprising an upper emitter layer and a lower emitter layer between the upper emitter layer and the base layer;
the collector and emitter layers being p doped;
the base layer being n doped; and
characterised in that the lower emitter layer has a larger bandgap than the base layer and is Ga x Al 1-x P, such that 0<x<1.