Semiconductor device
View Patent ↗To actualize a reduction in the on-resistance of a small surface mounted package having a power MOSFET sealed therein. A silicon chip is mounted on a die pad portion integrated with leads configuring a drain lead. The silicon chip has, on the main surface thereof, a source pad and a gate pad. The backside of the silicon chip configures a drain of a power MOSFET and bonded to the upper surface of a die pad portion via an Ag paste. A lead configuring a source lead is electrically coupled to the source pad via an Al ribbon, while a lead configuring a gate lead is electrically coupled to the gate pad via an Au wire.
1. A semiconductor device comprising:
a semiconductor chip mounted over a die pad portion of a lead frame and sealed in a resin package; and
an outer lead portion of the lead frame exposed from the resin package,
wherein the lead frame has a gate lead, a source lead, a drain lead and the die pad portion integrated with the drain lead,
wherein the semiconductor chip has, over a main surface thereof, a gate pad coupled to a gate electrode of a power MOSFET, and a source pad coupled to a source of the power MOSFET and having a greater area than the gate pad,
wherein a backside of the semiconductor chip forming a drain of the power MOSFET is bonded onto the die pad portion with an Ag paste,
wherein the source lead and the source pad are coupled via an Al ribbon, and
wherein the elastic modulus (Pa) of the Ag paste satisfies the following relation:
Pa<2.6×(adhesion thickness of Ag paste)/(displacement permitting ultrasonic bonding of Al ribbon)×(shear strength of Ag paste).
2. A semiconductor device comprising:
a semiconductor chip mounted over a die pad portion of a lead frame and sealed in a resin package; and
an outer lead portion of the lead frame exposed from the resin package,
wherein the lead frame has a gate lead, a source lead, a drain lead and the die pad portion integrated with the drain lead,
wherein the semiconductor chip has, over a main surface thereof, a gate pad coupled to a gate electrode of a power MOSFET, and a source pad coupled to a source of the power MOSFET and having a greater area than the gate pad,
wherein a backside of the semiconductor chip forming a drain of the power MOSFET is bonded onto the die pad portion with an Ag paste,
wherein the source lead and the source pad are coupled via an Al ribbon, and
wherein the elastic modulus of the Ag paste falls within a range of from 0.2 to 5.3 GPa and the shear strength is 8.5 MPa or greater.