IP Library Granted Patent US 9,317,255
Granted Patent B2
US 9,317,255 · App. 12/058,221 · Granted Apr 19, 2016

Automatic code transformation with state transformer monads

Inventors: Henricus Johannes Maria Meijer (Mercer Island, WA); John Wesley Dyer (Monroe, WA)
Assignee: Microsoft Technology Licensing, LCC
G06F8/24G06F8/30
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Quick Facts
Patent No.
US 9,317,255
App. No.
12/058,221
Granted
Apr 19, 2016
Kind
B2
Abstract

Stateful computations are transformed into stateless computations automatically to facilitate scalability. Programmers can write code in a traditional imperative stateful style, which is subsequently transformed automatically into a stateless, state transformer monadic style. After the transformation, state is passed as an additional argument in a call and returns as a new state as an additional result.

Claims (29)

1. A computer-readable memory device having computer-executable components stored thereon, the computer-executable components, comprising:

a component configured to receive inherently stateful code specified in an imperative programming language; and

a transform component configured to convert the stateful code into stateless code by transforming a form of a state associated with the stateful code into an argument explicitly representing the state in the stateless code, wherein the transform component is further configured to facilitate threading the argument explicitly representing the state through a sequence of stateless code operations with a same serialization infrastructure employed for both argument and result values, and wherein a first of the stateless code operations in the sequence is configured to accept a received state as an additional argument and return a modified state as an additional result to a second of the stateless code operations in the sequence.

2. The computer-readable memory device of claim 1 , wherein the transform component is configured to rewrite the stateful code in a stateless state transformation form.

3. The computer-readable memory device of claim 1 , wherein the transform component is configured to apply a wrapper to the stateful code to convert the stateful code into the stateless code.

4. The computer-readable memory device of claim 3 , wherein the wrapper converts an instance method into a static method.

5. The computer-readable memory device of claim 1 , further comprising a tier split component configured to split the stateful code for execution across multiple execution contexts.

6. The computer-readable memory device of claim 5 , wherein an intermediate state is stored on a client machine or a server.

7. The computer-readable memory device of claim 5 , wherein a first portion of an intermediate state is stored on a client and a second portion of the intermediate state is stored on a server.

8. The computer-readable memory device of claim 5 , wherein an intermediate state is stored on a dedicated subsystem that supports data replication.

9. The computer-readable memory device of claim 5 , further comprising a policy component configured to identify where an intermediate state is stored as a function of context information.

10. A code transformation method, comprising:

employing a processor to execute computer executable instructions stored on a computer readable storage medium to implement the following acts:

identifying a stateful computation in an imperative programming language; and

converting the stateful code into stateless code by transforming a form of a state associated with the stateful computation into an argument explicitly representing the state in the stateless code, wherein the argument explicitly representing the state is passed through a sequence of stateless code operations, wherein a first of the stateless code operations in the sequence is configured to accept a received state as an additional argument and return a modified state as an additional result to a second of the stateless code operations in the sequence, and wherein the state is threaded between code segments with a same serialization infrastructure employed for both argument and result values.

11. The method of claim 10 , comprising rewriting the stateful computation to enable state to be passed explicitly.

12. The method of claim 10 , comprising applying a wrapper to the stateful computation to transform the computation.

13. The method of claim 10 , further comprising splitting the computation for execution across multiple execution contexts.

14. The method of claim 13 , comprising specifying storage of an intermediate state on a client.

15. The method of claim 14 , comprising specifying client storage where offline operation is desirable.

16. The method of claim 13 , comprising specifying storage of an intermediate state on a server.

17. The method of claim 13 , comprising specifying storage of an intermediate state across a client and a server.

18. The method of claim 13 , further comprising specifying storage of an intermediate state separate from both a client and a server associated with computation execution.

19. A computer-readable memory device having computer-executable instructions for causing a computer to perform steps comprising:

acquiring an inherently stateful single tier computer application specified in an imperative language;

automatically generating distributed code from the single tier application; and

automatically converting the stateful code into stateless code by transforming a form of a state associated with a stateful portion of the distributed code into an argument explicitly representing the state in the stateless code to produce a scalable distributed application, wherein the argument explicitly representing the state is passed through a sequence of stateless code operations, wherein a first of the stateless code operations in the sequence is configured to accept a received state as an additional argument and return a modified state as an additional result to a second of the stateless code operations in the sequence, and wherein the state is threaded between code segments with a same serialization infrastructure employed for both argument and result values.

20. The computer-readable memory device of claim 1 , further comprising:

identifying where an intermediate state is stored as a function of context information.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 9, 2014
From: MICROSOFT CORPORATION
To: MICROSOFT TECHNOLOGY LICENSING, LLC
Reel/Frame 034542/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 28, 2008
From: MEIJER, HENRICUS JOHANNES MARIA; DYER, JOHN WESLEY
To: MICROSOFT CORPORATION
Reel/Frame 020721/0315 →
Continuity (1)
Related Publication 20090249310A1 · Oct 1, 2009