Frequency diverse discrete-time phase-lock device and apparatus
View Patent ↗A discrete-time phase lock loop (DTPLL) includes an analog section comprising a digital-to-analog converter (DAC) and an oscillator, operative to provide a clock signal based on an input from the DAC. The DTPLL also includes a digital signal processor (DSP). The DSP includes a loop controller state machine; a phase detector; a counter, operative to receive clock signals from the oscillator and to provide a count value to the phase detector; a divider, operative to receive a reference signal and to provide a reference pulse output to the phase detector; and a loop filter operative to provide a control effort value based on an output from the phase detector. Based on the phase error value, an output of the oscillator is changed to reduce the phase error to a steady state value.
1. A discrete-time phase lock loop (DTPLL), comprising:
an analog section comprising a digital-to-analog converter (DAC) and an oscillator, operative to provide a clock signal based on an input from the DAC; and
a digital signal processor (DSP) comprising:
a loop controller state machine;
a phase detector;
a counter, operative to receive clock signals from the oscillator and to provide a multi-bit count value to the phase detector;
a divider, operative to receive a reference signal and to provide a reference pulse output to the phase detector; and
a loop filter operative to provide a control effort value based on an output from the phase detector, wherein, based on the control effort value an output of the oscillator is changed to reduce a phase error to a steady state value.
2. A DTPLL as claimed in claim 1 , wherein the DSP comprises a field programmable gate array (FPGA).
3. A DTPLL as claimed in claim 2 , wherein the counter, the divider and the loop filter each comprise respective registers having operational parameters.
4. A DTPLL as claimed in claim 1 , wherein the DSP further comprises a phase lock detector, operative to compare the phase error with a threshold and to provide an output to the loop controller state machine indicative of the lock state of the DTPLL.
5. A DTPLL as claimed in claim 1 , wherein the loop filter comprises a proportional integral (PI) filter.
6. A DTPLL as claimed in claim 1 , wherein the loop filter comprises a proportional integral derivative (PID) filter.
7. A DTPLL as claimed in claim 6 , wherein the PID filter provides a signal to the DAC, which drives the oscillator based on the control effort.
8. A DTPLL as claimed in claim 7 , wherein the signal from the PID filter further comprises a control effort further comprises a finite bit word, which is added to a calibration value at an adder, and the output from the adder is representative of a change required in an output of the oscillator.
9. A DTPLL as claimed in claim 1 , wherein the counter has a maximum value, N, and the divider divides by a reference value, M, and a phase lock condition is approximately: (f o /N)=(f ref /M), where f o is an oscillator frequency and f ref is a reference clock frequency.
10. A DTPLL as claimed in claim 1 , wherein the oscillator is a voltage controlled oscillator (VCO).
11. An instrument, comprising:
a discrete-time phase lock loop (DTPLL), comprising:
an analog section comprising a digital-to-analog converter (DAC) and an oscillator, operative to provide a clock signal based on an input from the DAC; and
a digital signal processor (DSP) comprising:
a loop controller state machine;
a phase detector;
a counter, operative to receive clock signals from the oscillator and to provide a multi-bit count value to the phase detector;
a divider, operative to receive a reference signal and to provide a reference pulse output to the phase detector; and
a loop filter operative to provide a control effort value based on an output from the phase detector, wherein, based on the control effort value an output of the oscillator is changed to reduce a phase error to a steady state value.
12. An instrument as claimed in claim 11 , wherein the DSP comprises a field programmable gate array (FPGA).
13. An instrument as claimed in claim 12 , wherein the counter, the divider and the loop filter each comprise respective registers having operational parameters.
14. An instrument as claimed in claim 11 , wherein the DSP further comprises a phase lock detector, operative to compare the phase error with a threshold and to provide an output to the loop controller state machine indicative of the lock state of the DTPLL.
15. An instrument as claimed in claim 11 , wherein the loop filter comprises a proportional integral (PI) filter.
16. An instrument as claimed in claim 11 , wherein the loop filter comprises a proportional integral derivative (PID) filter.
17. An instrument as claimed in claim 16 , wherein the PID filter provides a signal to the DAC, which drives the oscillator based on the control effort.
18. An instrument as claimed in claim 17 , wherein the signal from the PID filter further comprises a control effort further comprising a finite bit word, which is added to a calibration value at an adder, and the output from the adder is representative of a change required in an output of the oscillator.
19. An instrument as claimed in claim 11 , wherein the counter has a maximum value, N, and the divider divides by a reference value, M, and a phase lock condition is approximately: (f o /N)=(f ref /M), where f o is an oscillator frequency and f ref is a reference clock frequency.
20. An instrument as claimed in claim 11 , wherein the instrument is a measurement instrument.
21. An instrument as claimed in claim 20 , wherein the measurement instrument is a handheld instrument.