Analog phase-locked loop
View Patent ↗Aspects of the present invention are related, in general, to Type-III phase-locked loops. In particular, aspects of the present invention relate to analog Type-III phase-locked loop arrangements comprising at least two signal paths, wherein each signal path may correspond to a bandwidth partition and may be selected by a selector according to a bandwidth parameter value. According to one aspect of the present invention, a first signal path may correspond to a fast loop (wide closed-loop bandwidth), and a second signal path may correspond to a slow loop (narrow closed-loop bandwidth).
1. An analog phase-locked loop arrangement, said analog phase-locked loop arrangement comprising:
a) a phase detector for providing an error signal representative of the difference in phase between an input reference signal and an output signal of said analog phase-locked loop arrangement;
b) a first selector for establishing a connection between said error signal and a first signal path when a first bandwidth parameter value is selected and for establishing a connection between said error signal and a second signal path when a second bandwidth parameter value is selected, wherein:
i) said first signal path comprises:
(1) a first first-signal-path integrator for integrating said error signal, thereby producing a first-signal-path integrated signal;
(2) a second first-signal-path integrator for integrating said first-signal-path integrated signal, thereby producing a first-signal-path error-voltage signal; and
(3) a first-signal-path voltage-controlled oscillator responsive to said first-signal-path error-voltage signal, thereby producing a first-signal-path output signal; and
ii) said second signal path comprises:
(1) a first second-signal-path integrator for integrating said error signal, thereby producing a second-signal-path integrated signal;
(2) a second second-signal-path integrator for integrating said second-signal-path integrated signal, thereby producing a second-signal-path error-voltage signal; and
(3) a second-signal-path voltage-controlled oscillator responsive to said second-signal-path error-voltage signal, thereby producing a second-signal-path output signal;
c) a second selector for selecting said first-signal-path output signal as said output signal when said first bandwidth parameter value is selected and for selecting said second-signal-path output signal as said output signal when said second bandwidth parameter value is selected; and
d) a feedback connection connecting said output signal to said phase detector.
2. An analog phase-locked loop arrangement as described in claim 1 , wherein said input reference signal is a clock signal comprising a jitter component and a wander component.
3. An analog phase-locked loop arrangement as described in claim 1 , wherein:
a) said first-signal-path voltage-controlled oscillator comprises a wide-range voltage-controlled oscillator; and
b) said second-signal-path voltage-controlled oscillator comprises a narrow-range voltage-controlled oscillator.
4. An analog phase-locked loop arrangement as described in claim 1 , wherein:
a) said first signal path is associated with a first plurality of frequencies, wherein each frequency in said first plurality of frequencies is less than a first demarcation frequency; and
b) said second signal path is associated with a second plurality of frequencies, wherein each frequency in said second plurality of frequencies is less than a second demarcation frequency.
5. An analog phase-locked loop arrangement as described in claim 1 , wherein:
a) said first first-signal-path integrator and said second first-signal-path integrator provide a positive phase margin at unity gain for said first signal path; and
b) said first second-signal-path integrator and said second second-signal-path integrator provide a positive phase margin at unity gain for said second signal path.
6. A system for providing a time reference to a measurement device for an eye diagram, said system comprising:
a) an analog phase-locked loop arrangement, said analog phase-locked loop arrangement comprising:
i) a phase detector for providing an error signal representative of the difference in phase between an input reference signal and an output signal of said analog phase-locked loop arrangement;
ii) a first selector for establishing a connection between said error signal and a fast-loop signal path when a first bandwidth parameter value is selected and for establishing a connection between said error signal and a slow-loop signal path when a second bandwidth parameter value is selected, wherein:
(1)said fast-loop signal path comprises:
(a) a first fast-loop-path integrator for integrating said error signal, thereby producing a fast-loop-path integrated signal;
(b) a second fast-loop-path integrator for integrating said fast-loop-path integrated signal, thereby producing a fast-loop-path error-voltage signal; and
(c) a fast-loop-path voltage-controlled oscillator responsive to said fast-loop-path error-voltage signal, thereby producing a fast-loop output signal; and
(2) said slow-loop signal path comprises:
(a) a first slow-loop-path integrator for integrating said error signal, thereby producing a slow-loop-path integrated signal;
(b) a second slow-loop-path integrator for integrating said slow-loop-path integrated signal, thereby producing a slow-loop-path error-voltage signal; and
(c) a slow-loop-path voltage-controlled oscillator responsive to said slow-loop-path error-voltage signal, thereby producing a slow-loop output signal;
iii) a second selector for selecting said fast-loop output signal as said output signal when said first bandwidth parameter value is selected and for selecting said slow-loop output signal as said output signal when said second bandwidth parameter is selected; and
iv) a feedback connection connecting said output signal to said phase detector; and
b) an access port for connecting said output signal to said measurement device.
7. A system as described in claim 6 , wherein:
a) said first fast-loop-path integrator and said second fast-loop-path integrator provide a positive phase margin at unity gain for said fast-loop signal path; and
b) said first slow-loop-path integrator and said second slow-loop-path integrator provide a positive phase margin at unity gain for said slow-loop signal path.
8. A system as described in claim 6 , wherein said measurement device is an oscilloscope.
9. A system as described in claim 6 , wherein said input reference signal is a clock signal comprising a jitter component and a wander component.
10. A system as described in claim 6 , wherein:
a) said fast-loop-path voltage-controlled oscillator comprises a wide-range voltage-controlled oscillator; and
b) said slow-loop-path voltage-controlled oscillator comprises a narrow-range voltage-controlled oscillator.
11. A system as described in claim 6 , wherein:
a) said fast-loop signal path is associated with a first plurality of frequencies, wherein each frequency in said first plurality of frequencies is less than a first demarcation frequency;
b) said first fast-loop-path integrator is a first wide-bandwidth integrator;
c) said second fast-loop-path integrator is a second wide-bandwidth integrator;
d) said slow-loop signal path is associated with a second plurality of frequencies, wherein each frequency in said second plurality of frequencies is less than a second demarcation frequency;
e) said first slow-loop-path integrator is a first narrow-bandwidth integrator;
f) said second slow-loop-path integrator is a second narrow-bandwidth integrator; and
g) said first demarcation frequency is greater than said second demarcation frequency.
12. An analog phase-locked loop arrangement, said analog phase-locked loop arrangement comprising:
a) a path selector for establishing a connection between an input reference signal and a first signal path and an output signal and said first signal path when a first bandwidth parameter value is selected and for establishing a connection between said input reference signal and a second signal path and said output signal and said second signal path when a second bandwidth parameter value is selected, wherein:
i) said first signal path comprises:
(1) a first-signal-path phase detector for providing an first-signal-path error signal representative of the difference in phase between said input reference signal and said output signal;
(2) a first first-signal-path integrator for integrating said first-signal-path error signal, thereby producing a first-signal-path integrated signal;
(3) a second first-signal-path integrator for integrating said first-signal-path integrated signal, thereby producing a first-signal-path error-voltage signal; and
(4) a first-signal-path voltage-controlled oscillator responsive to said first-signal-path error-voltage signal, thereby producing a first-signal-path output signal; and
ii) said second signal path comprises:
(1) a second-signal-path phase detector for providing an second-signal-path error signal representative of the difference in phase between said input reference signal and said output signal;
(2) a first second-signal-path integrator for integrating said second-signal-path error signal, thereby producing a second-signal-path integrated signal;
(3) a second second-signal-path integrator for integrating said second-signal-path integrated signal, thereby producing a second-signal-path error-voltage signal; and
(4) a second-signal-path voltage-controlled oscillator responsive to said second-signal-path error-voltage signal, thereby producing a second-signal-path output signal;
b) an output selector for selecting said first-signal-path output signal as said output signal when said first bandwidth parameter value is selected and for selecting said second-signal-path output signal as said output signal when said second bandwidth parameter value is selected; and
c) a feedback connection connecting said output signal to said path selector.
13. An analog phase-locked loop arrangement as described in claim 12 , wherein said input reference signal is a clock signal comprising a jitter component and a wander component.
14. An analog phase-locked loop arrangement as described in claim 12 , wherein:
a) said first-signal-path voltage-controlled oscillator comprises a wide-range voltage-controlled oscillator; and
b) said second-signal-path voltage-controlled oscillator comprises a narrow-range voltage-controlled oscillator.
15. An analog phase-locked loop arrangement as described in claim 12 , wherein:
a) said first signal path is associated with a first plurality of frequencies, wherein each frequency in said first plurality of frequencies is less than a first demarcation frequency; and
b) said second signal path is associated with a second plurality of frequencies, wherein each frequency in said second plurality of frequencies is less than a second demarcation frequency.
16. An analog phase-locked loop arrangement as described in claim 12 , wherein:
a) said first first-signal-path integrator and said second first-signal-path integrator provide a positive phase margin at unity gain for said first signal path; and
b) said first second-signal-path integrator and said second second-signal-path integrator provide a positive phase margin at unity gain for said second signal path.